US4667303A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital integrated circuit comprising complementary field effect transistors
Assignee: US Philips Corp
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Filing: 1984-04-13
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Granted: 1987-05-19
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Expires: 2004-04-13
Abstract
Abstract Digital integrated C-MOS circuit in which two cross-coupled P-MOS transistors are connected by two separation transistors (N-MOS) to two complementary switching N-MOS transistor logic networks. The gate electrodes of the separation transistor are connected to a reference voltage source. The switching speed of the C-MOS circuit is increased in that (a) the voltage sweep across the logic networks is reduced; (b) each P-MOS transistor, which is connected by a separation transistor to a junction of the logic network to be charged, is slightly conducting and so is "ready" to charge such junction, and (c) the separation transistor between the fully conducting P-MOS transistor and the junction to be discharged in the second logic network constitutes a high impedance which prevents the conducting P-MOS transistor from charging that junction.
Inventors
- 👤 Leonardus C. M. G. Pfennings
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
291 words
In a digital integrated circuit comprising a plurality of insulated gate field effect transistors (IGFETs) and having a pair of supply voltage terminals and a pair of output terminals, the improvement consisting of: first and second switching IGFETs (IGFETs 1 and 2) of a first conductivity type, the source-drain paths of which are respectively connected between one of said supply voltage terminals and a first and second of said output terminals, respectively; first and second logic circuits respectively comprising a plurality of IGFETs of a second conductivity type, said first logic circuit being connected between the other of said supply voltage terminals and the gate electrode of switching IGFET 2 and said second logic network being connected between said other supply voltage terminal and the gate electrode of switching IGFET 1; the gate electrodes of the IGFETs in said first and second logic networks receiving complementary logic signals, whereby complementary logic signals are supplied by said first and second logic networks to the gate electrodes of switching IGFET 2 and switching IGFET 1, respectively; first and second IGFETs (IGFETs 3 and 4) of said second conductivity type respectively connecting said first and second logic circuits to said first and second output terminals, respectively; and means for supplying a substantially constant reference voltage which is less than said supply voltage to the gate electrodes of IGFETs 3 and 4; whereby the voltage sweep of the logic signals supplied to the gate electrodes of switching IGFETs 1 and 2 in response to the logic signals received by said first and second logic networks are reduced by an amount equal to said reference voltage, and complementary output signals are produced at said first and second output terminals in response to said received logic signals.
Claim 2
Dependent Claim
291 words
In a digital integrated circuit comprising a plurality of insulated gate field effect transistors (IGFETs) and having a pair of supply voltage terminals and a pair of output terminals, the improvement consisting of: first and second switching IGFETs (IGFETs 1 and 2) of a first conductivity type, the source-drain paths of which are respectively connected between one of said supply voltage terminals and a first and second of said output terminals, respectively; first and second logic circuits respectively comprising a plurality of IGFETs of a second conductivity type, said first logic circuit being connected between the other of said supply voltage terminals and the gate electrode of switching IGFET 2 and said second logic network being connected between said other supply voltage terminal and the gate electrode of switching IGFET 1; the gate electrodes of the IGFETs in said first and second logic networks receiving complementary logic signals, whereby complementary logic signals are supplied by said first and second logic networks to the gate electrodes of switching IGFET 2 and switching IGFET 1, respectively; first and second IGFETs (IGFETs 3 and 4) of said second conductivity type respectively connecting said first and second logic circuits to said first and second output terminals, respectively; and means for supplying a substantially constant reference voltage which is less than said supply voltage to the gate electrodes of IGFETs 3 and 4; whereby the voltage sweep of the logic signals supplied to the gate electrodes of switching IGFETs 1 and 2 in response to the logic signals received by said first and second logic networks are reduced by an amount equal to said reference voltage, and complementary output signals are produced at said first and second output terminals in response to said received logic signals.
Claim 3
Dependent Claim
43 words
A digital integrated circuit as claimed in claim 1, characterized in that the width/length ratios of the channels of IGFET 3 and IGFET 4 are respectively smaller than such ratios for any of the IGFETs in said first and second logic networks, respectively.
Claim 4
Dependent Claim
35 words
A digital integrated circuit as claimed in claim 1, characterized in that the reference voltage supplied to the gate electrodes of IGFETs 3 and 4 is adjustable to any of at least two voltage levels.
Claim 5
Dependent Claim
215 words
A digital integrated circuit as claimed in claim 1, 2 or 3, wherein the output signals produced at said first and second output terminals constitute summations of the logic signals received by said first and second logic networks, and wherein: said first and second logic networks each comprise first and second parallel branches of three series-connected IGFETs in each branch, the junction between the first and second IGFETs (IGFETs 5 and 6) in the first branch of the first logic network being connected to the junction between the first and second IGFETs (IGFETs 7 and 8) in the second branch of the first logic network, and the junction between the first and second IGFETs (IGFETs 9 and 10) in the first branch of the second logic network being connected to the junction between the first and second IGFETs (IGFETs 11 and 12) in the second branch of the second logic network; the source-drain paths of IGFETs 5 and 9 are connected to IGFET 3 and the source-drain paths of IGFETs 7 and 11 are connected to IGFET 4; the successive IGFETs in the first branch of each of said logic networks receiving gate signals which are complementary to the gate signals received by the corresponding IGFETs in the second branch of the same logic network.
Claim 6
Dependent Claim
272 words
A digital integrated circuit as claimed in claim 1, 2 or 3, wherein the output signals produced at said first and second output terminals constitute summations of the logic signals received by said first and second logic networks, and wherein: said first and second logic networks each comprise first and second parallel branches of two series-connected IGFETs in each branch, the junction between the first and second IGFETs (IGFETs 5 and 6) in the first branch of the first logic network being connected to the junction between the first and second IGFETs (IGFETs 7 and 8) in the second branch of the first logic network, and the junction between the first and second IGFETs (IGFETs 9 and 10) in the first branch of the second logic network being connected to the junction between the first and second IGFETs (IGFETs 11 and 12) in the second branch of the second logic network; the source-drain paths of IGFETs 5 and 9 are connected to IGFET 3 and the source-drain paths of IGFETs 7 and 11 are connected to IGFET 4; the gate electrodes of the successive IGFETs in the first branch of each of said logic networks receive logic signals which are complementary to the logic signals received by the gate electrodes of the corresponding IGFETs in the second branch of the same logic network; and the first branch of the first logic network further comprises a third IGFET (IGFET 13) series-connected therein and the second branch of the second logic network further comprises a third IGFET (IGFET 14) series-connected therein, the gate electrodes of IGFETs 13 and IGFET 14 receiving complementary logic signals.
Claim 7
Dependent Claim
172 words
A digital integrated circuit as claimed in claim 1, 2 or 3, wherein the output signals produced at said first and second output terminals constitute carries of summations of the logic signals received by said first and second logic networks, and wherein: said first and second logic networks each comprise first and second parallel branches of two series-connected IGFETs in each branch, the logic signals received by the gate electrodes of the first and second transistors in the first and second branches of the first logic network being complementary to the logic signals received by the gate electrodes of the corresponding IGFETs in the first and second branches, respectively, of the second logic network; and a further IGFET (IGFET 5) is connected in parallel with the second IGFET in the second branch of the first logic network and a further IGFET (IGFET 6) is connected in parallel with the second IGFET in the second branch of the second logic network, the gate electrodes of IGFETs 5 and 6 receiving complementary logic signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-18 | 1990-11-17 | 1991-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-18 | 1994-11-17 | 1995-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-18 | 1998-11-17 | 1999-05-19 | $7700.00 | Window Closed / Lapsed |