US4667232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronizing pulse restoration circuit
Assignee: Zenith Electronics LLC
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Filing: 1985-04-11
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Granted: 1987-05-19
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Expires: 2005-04-11
Abstract
Abstract A decoder for a television signal encrypted with randomly inverted video and randomly suppressed sync pulses includes inverting and noninverting amplifiers for inverting the inverted video and a sync pulse restoration circuit for restoring suppressed sync pulses, all under control of decoder logic. A comparator is coupled to the noninverting amplifier and changes its output voltage in the presence of signal portions extending beyond the mid sync level of the video signal. The output of the comparator is connected to the emitter of a transistor that has its collector supplied through a voltage divider load from a source of blanking level voltage. The junction of the voltage divider receives the decoded video signal. The transistor is driven conductive in response to flyback pulses, corresponding to the occurrence of sync pulses, applied to its base. The transistor conducts only during sync pulse intervals and the level of the decoded video signal during these intervals is brought to a common point, thus restoring all sync tips to the same height. For negative noise spikes, the transistor is not driven conductive and the level of the decoded video signal is held at blanking level.
Inventors
- 👤 Michael E. Long
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:15
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/16; H04N7/167; H04N7/171; H04N7/1716; H04N7/1713
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
99 words
A sync pulse restoration circuit for a decoder comprising. means for developing a baseband video signal that includes restored sync pulses and normal sync pulses of different heights; comparator means for stripping portions of said signal that extend beyond a mid sync level to video blanking level, said mid sync level corresponding to a level between said video blanking level and sync tip level; and means for replacing stripped signal portions, corresponding only to sync pulses, with pulses of uniform height whereby a restored siognal of uniform sync tip level, without noise exceeding said video blanking level, is produced.
Claim 2
Dependent Claim
99 words
A sync pulse restoration circuit for a decoder comprising. means for developing a baseband video signal that includes restored sync pulses and normal sync pulses of different heights; comparator means for stripping portions of said signal that extend beyond a mid sync level to video blanking level, said mid sync level corresponding to a level between said video blanking level and sync tip level; and means for replacing stripped signal portions, corresponding only to sync pulses, with pulses of uniform height whereby a restored siognal of uniform sync tip level, without noise exceeding said video blanking level, is produced.
Claim 3
Dependent Claim
73 words
The circuit of claim 1 further including: a transistor coupled to the output of said comparator means, and having a load circuit; a video signal processor for supply a decoded video signal to said load circuit, said transistor being nonconductive except during occurrence of a sync pulse; and means responsive to said comparator determining a signal in excess of said mid sync level for isolating said video signal processor from said load circuit.
Claim 4
Dependent Claim
54 words
The circuit of claim 2 wherein said transistor is supplied with flyback pulses for driving it conductive only during occurrence of sync pulses, said load circuit establishing a fixed voltage for said decoded video signal during conduction of said transistor whereby said replaced sync pulses in said decoded video signal are of uniform height.
Claim 5
Dependent Claim
135 words
In a television decoder circuit of the type including a suppressed sync pulse restorer and a video inverter and logic means for controlling operation of the restorer and the inverter to develop a decoded baseband video signal with both restored and normal sync pulses, the improvement comprising: comparator means for determining the presence of signal portions beyond a mid sync level, said mid sync level corresponding to a level between blanking level and sync tip level; means for stripping signal portions in excess of said mid sync level to video blanking level; and means operable only during the occurrence of a sync pulse and responsive to said comparator means for replacing both restored and normal sync pulses with new sync pulses of constant height and for eliminating noise in excess of said video blanking level.
Claim 6
Dependent Claim
135 words
In a television decoder circuit of the type including a suppressed sync pulse restorer and a video inverter and logic means for controlling operation of the restorer and the inverter to develop a decoded baseband video signal with both restored and normal sync pulses, the improvement comprising: comparator means for determining the presence of signal portions beyond a mid sync level, said mid sync level corresponding to a level between blanking level and sync tip level; means for stripping signal portions in excess of said mid sync level to video blanking level; and means operable only during the occurrence of a sync pulse and responsive to said comparator means for replacing both restored and normal sync pulses with new sync pulses of constant height and for eliminating noise in excess of said video blanking level.
Claim 7
Dependent Claim
81 words
The decoder of claim 4 further including: an output terminal for the decoded video signal; a transistor including resistive means in its load circuit, said resistive means being coupled to said output terminal; means supplying said resistive means with a voltage corresponding to a desired blanking level for said decoded video signal; means coupling the output of said comparator to said transistor; and means supplying the input of said transistor with a turn on voltage when a sync pulse is determined.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-18 | 1990-11-17 | 1991-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-18 | 1994-11-17 | 1995-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-18 | 1998-11-17 | 1999-05-19 | $7700.00 | Window Closed / Lapsed |