Energy management/dimming system and control

Claim 3

The method of claim 1 wherein said predetermined time period corresponds to a half-cycle of the current supplied by said AC source, and wherein each of said current measurements is the integral of current flowing during the portions of a respective half-cycle outside of said notch period.

Claim 4

The method of claim 2 wherein said plurality of current measurements are obtained from four consecutive half-cycles.

Claim 5

The method of claim 1 wherein steps 1-4 are continuously repeated.

Claim 6

The method of claim 4 further comprising the step of periodically checking for a change in said level command.

Claim 7

The method of claim 5 further comprising the steps of: (A) finding the difference between the latest command current reference and the command current reference corresponding to said light level command; (B) comparing the difference from step A to a predetermined step size constant; and (C) if said difference is greater than said constant, then altering said command current reference by an amount equal to said constant, else altering said command current reference by an amount equal to said difference; whereby a ramping effect of the light output results whenever shifting between discrete light output settings of said level command.

Claim 8

The method of claim 4, after said error calculating step, further comprising the step of: digitally filtering said error relative to the previous alteration in said notch period, said filtered error providing the amount by which said notch period is to be altered.

Claim 10

The method of claim 8 wherein A has a value of 0.75 and B has a value of 0.25.

Claim 11

The method of claim 1 wherein said predetermined time period corresponds to a half-cycle of the current supplied by said AC source, said method further comprising the steps of: sensing alternate zero crossings of said current; and electronically counting to determine the midpoints between said sensed alternate zero crossings; whereby the timing of said half-cycles is established without errors caused by DC offset voltages.

Claim 12

The method of claim 1, after said averaging step, further comprising the step of shutting down said dimming system if said average is below a predetermined value.

Claim 13

A dimming control circuit in a fluorescent lamp dimming system, said dimming system being adapted to be connected to a fluorescent lighting system including a ballast, fluorescent lamps and an AC source, said dimming system including a switch for connecting in series with said ballast, said switch adapted to turn on and off at a high frequency during a notch period within each half-cycle of current supplied to said ballast by said AC source and adapted to turn on during the portions of each half-cycle outside of said notch period, said dimming control circuit comprising: signal processing means for coupling to said switch, said signal processing means providing a first output signal proportional to the instantaneous current flowing through said switch from said AC source to said ballast and a second output signal for indicating zero crossings of said instantaneous current; integrating means coupled to said signal processing means for integrating said first output signal to provide a current integral, the timing of the integration being provided according to said second output signal; comparing means coupled to said integrating means for comparing said current integral to a command current reference and providing an error value; timing means coupled to said signal processing means for receiving said second output signal and adapted to be coupled to said switch, said timing means for establishing said notch period and the high frequency switching of said switch during said notch period; and logic means coupled to said signal processing means, said comparing means and said timing means, said logic means adapted to receive a light level command signal, said logic means providing said command current reference to said comparison means based on said light level command signal, and said logic means providing counting values to said timing means based on said command current reference and said error value.

Claim 14

A dimming control circuit in a fluorescent lamp dimming system, said dimming system being adapted to be connected to a fluorescent lighting system including a ballast, fluorescent lamps and an AC source, said dimming system including a switch for connecting in series with said ballast, said switch adapted to turn on and off at a high frequency during a notch period within each half-cycle of current supplied to said ballast by said AC source and adapted to turn on during the portions of each half-cycle outside of said notch period, said dimming control circuit comprising: signal processing means for coupling to said switch, said signal processing means providing a first output signal proportional to the instantaneous current flowing through said switch from said AC source to said ballast and a second output signal for indicating zero crossings of said instantaneous current; integrating means coupled to said signal processing means for integrating said first output signal to provide a current integral, the timing of the integration being provided according to said second output signal; comparing means coupled to said integrating means for comparing said current integral to a command current reference and providing an error value; timing means coupled to said signal processing means for receiving said second output signal and adapted to be coupled to said switch, said timing means for establishing said notch period and the high frequency switching of said switch during said notch period; and logic means coupled to said signal processing means, said comparing means and said timing means, said logic means adapted to receive a light level command signal, said logic means providing said command current reference to said comparison means based on said light level command signal, and said logic means providing counting values to said timing means based on said command current reference and said error value.

Claim 15

The dimming control circuit of claim 12 wherein said comparing means computes an average error value over four consecutive half-cycles.

Claim 16

The dimming control circuit of claim 12 wherein said signal processing means indicates alternate zero crossings via said second output signal, and wherein said timing means further includes means for determining the midpoints between said alternate zero crossings.

Claim 17

The dimming control circuit of claim 12 further comprising error filtering means coupled to said comparing means and to said logic means for filtering said error value relative to the previously filtered error value.

Claim 18

The dimming control circuit of claim 15 further comprising notch blanking means coupled to said signal processing means, said integrating means and said timing means, said notch blanking means reducing the input signal to said integrating means to zero during said notch period.

Claim 19

The dimming control circuit of claim 12 further comprising notch blanking means coupled to said signal processing means, said integrating means and said timing means, said notch blanking means reducing the input signal to said integrating means to zero during said notch period.

Claim 20

The dimming control circuit of claim 12 further comprising driving means for coupling between said timing means and said switch for turning on and off said switch in accordance with outputs of said digital counters.

Claim 21

The dimming control circuit of claim 12 further comprising scaling means coupled to said signal processing means, said integrating means and said logic means for normalizing said first output signal of said signal processing means.

Claim 22

A fluorescent lamp dimming system for connecting to a fluorescent lighting system, said lighting system including a ballast, fluorescent lamps and an AC source, said timming system comprising: a switch for connecting in series with said ballast, said switch adapted to turn on and off at a high frequency during a notch period within each half-cycle of current supplied to said ballast by said AC source and adapted to turn on during the portions of each half-cycle outside of said notch period; signal processing means coupled to said switch, said signal processing means providing a first output signal proportional to the instantaneous current flowing through said switch from said AC source to said ballast and a second output signal for indicating zero crossings of said instantaneous current; integrating means coupled to said signal processing means for integrating said first output signal to provide a current integral, the timing of the integration being provided according to said second output signal; comparing means coupled to said integrating means for comparing said current integral to a command current reference and providing an error value; timing means coupled to said signal processing means for receiving said second output signal and adapted to be coupled to said switch, said timing means including digital counters for establishing said notch period and the high frequency switching of said switch during said notch period; and logic means coupled to said signal processing means, said comparing means and said timing means, said logic means adapted to receive a light level command signal, said logic means providing said command current reference to said comparison means based on said light level command signal, and said logic means providing counting values to said digital counters based on said command current reference and said error value.

Claim 23

A fluorescent lamp dimming system for connecting to a fluorescent lighting system, said lighting system including a ballast, fluorescent lamps and an AC source, said timming system comprising: a switch for connecting in series with said ballast, said switch adapted to turn on and off at a high frequency during a notch period within each half-cycle of current supplied to said ballast by said AC source and adapted to turn on during the portions of each half-cycle outside of said notch period; signal processing means coupled to said switch, said signal processing means providing a first output signal proportional to the instantaneous current flowing through said switch from said AC source to said ballast and a second output signal for indicating zero crossings of said instantaneous current; integrating means coupled to said signal processing means for integrating said first output signal to provide a current integral, the timing of the integration being provided according to said second output signal; comparing means coupled to said integrating means for comparing said current integral to a command current reference and providing an error value; timing means coupled to said signal processing means for receiving said second output signal and adapted to be coupled to said switch, said timing means including digital counters for establishing said notch period and the high frequency switching of said switch during said notch period; and logic means coupled to said signal processing means, said comparing means and said timing means, said logic means adapted to receive a light level command signal, said logic means providing said command current reference to said comparison means based on said light level command signal, and said logic means providing counting values to said digital counters based on said command current reference and said error value.

Claim 24

The dimming system of claim 20 wherein said comparing means is adapted to compute an average error value over four consecutive half-cycles.

Claim 25

The dimming system of claim 20 wherein said signal processing means indicates alternate zero crossings via said second output signal, and wherein said timing means further includes a digital counter for determining the midpoints between said alternate zero crossings.

Claim 26

The dimming system of claim 20 further comprising error filtering means coupled to said comparing means and to said logic means for filtering said error value relative to the previous filtered error value.

Claim 27

The dimming system of claim 23 further comprising notch blanking means coupled to said signal processing means, to said integrating means and to said timing means, said notch blanking means reducing the input signal to said integrating means to zero during said notch period.

Claim 28

The dimming system of claim 20 further comprising notch blanking means coupled to said signal processing means, said integrating means and said timing means, said notch blanking means reducing the input signal to said integrating means to zero during said notch period.

Claim 29

The dimming system of claim 20 further comprising driving means coupled between said timing means and said switch for turning on and off said switch in accordance with outputs of said digital counters.

Claim 30

The dimming system of claim 20 further comprising scaling means coupled to said signal processing means, to said integrating means and to said logic means, for normalizing said first output signal of said signal processing means.

Claim 31

The dimming system of claim 20 further comprising clamping means adapted to be connected in parallel with said ballast for clamping the voltage across said ballast to a predetermined value.

Claim 32

A fluorescent lamp dimming system for connecting to a fluorescent lighting system, said lighting system including a ballast, fluorescent lamps and an AC source, said dimming system comprising: microprocessor means for controlling the operation of said dimming system, said microprocessor means including a clock, a stored program and data memory, said microprocessor means being responsive to an interrupt; a data bus connected to said microprocessor means; an address bus connected to said microprocessor means; a timing controller connected to said data bus and to said address bus, and coupled to said microprocessor means, said timing controller including a notch digital counter and a pulse digital counter, said notch digital counter adapted to generate a notch period, the output of said notch digital counter having a first output state during said notch period and having a second output state outside of said notch period, said pulse digital counter adapted to generate high frequency pulses during said notch period, the counting values of said notch and pulse digital counters being loaded by said microprocessor means via said data bus and said address bus; and interface means connected to said microprocessor means for receiving an externally supplied light level command and for providing said command to said microprocessor means.

Claim 33

A fluorescent lamp dimming system for connecting to a fluorescent lighting system, said lighting system including a ballast, fluorescent lamps and an AC source, said dimming system comprising: microprocessor means for controlling the operation of said dimming system, said microprocessor means including a clock, a stored program and data memory, said microprocessor means being responsive to an interrupt; a data bus connected to said microprocessor means; an address bus connected to said microprocessor means; a timing controller connected to said data bus and to said address bus, and coupled to said microprocessor means, said timing controller including a notch digital counter and a pulse digital counter, said notch digital counter adapted to generate a notch period, the output of said notch digital counter having a first output state during said notch period and having a second output state outside of said notch period, said pulse digital counter adapted to generate high frequency pulses during said notch period, the counting values of said notch and pulse digital counters being loaded by said microprocessor means via said data bus and said address bus; and interface means connected to said microprocessor means for receiving an externally supplied light level command and for providing said command to said microprocessor means.

Claim 34

The dimming system of claim 29 further comprising a first logic gate coupled to said timing controller for combining the outputs of said notch and pulse digital counters to generate a gate signal.

Claim 35

The dimming system of claim 30 further comprising: current zero detector means adapted to be coupled to said lighting system for generating a pulse signal at every other zero crossing of the low frequency component of current from said AC source; a zero-crossing digital counter in said timing controller for generating a pulse signal at alternate zero crossings; and a second logic gate for combining the pulse signals from said current zero detector means and said zero-crossing digital counter, the output of said second logic gate being connected to said microprocessor means so as to generate an interrupt in said microprocessor means at every zero crossing pulse from said second logic gate.

Claim 36

The dimming system of claim 31 further comprising: current converting means adapted to be coupled to said lighting system for generating an output signal having an instantaneous frequency proportional to the instantaneous magnitude of the current flowing to said ballast; an integral digital counter in said timing controller coupled to said current converting means for generating the integral of said current; and a third logic gate coupling the output of said current converting means to said integral digital counter, said third logic gate being connected to the output of said notch digital counter, said third logic gate transmitting said current converting means output signal outside of said notch period.

Claim 37

The dimming system of claim 31 wherein said current zero detector means is comprised of a flip-flop for generating said pulse signal at its inverted output and wherein said timing controller includes an inhibit digital counter for setting said flip-flop between alternate zero crossings.

Claim 38

The dimming system of claim 32 further comprising a switch for connecting in series with said ballast, said switch adapted to be turned on and off in accordance with said gate signal.

Claim 39

The dimming system of claim 34 further comprising opto-coupling means for coupling said gate signal to said switch.

Claim 40

The dimming system of claim 35 further comprising a clamp switch for connecting in parallel with said ballast.

Claim 41

A fluorescent lamp dimming system for connecting to a fluorescent lighting system, said lighting system including a ballast, fluorescent lamps and an AC source, said dimming system comprising: a switch for connecting in series with said ballast, said switch adapted to turn on and off at a high frequency during a notch period within each half-cycle of current supplied to said ballast by said AC source and adapted to turn on during the portions of each half-cycle outside of said notch period; a high voltage integrated circuit connected to said switch including a driver circuit for connecting to the control electrode of said switch, detector means for generating current zero signals, and current means for generating a current signal having a magnitude proportional to the instantaneous current flowing in said switch; a matrix chip connected to said high voltage integrated circuit including integrating means for integrating said current signal, notch timing means for generating said notch period, pulse means for generating pulses at said high frequency during said notch period, and logic gate means for combining the outputs of said notch timing means and said pulse means to generate a gate signal for coupling to said drive circuit; and a microprocessor connected to said matrix chip for controlling said matrix chip in accordance with a desired light level of said fluorescent lamps.

Claim 42

A fluorescent lamp dimming system for connecting to a fluorescent lighting system, said lighting system including a ballast, fluorescent lamps and an AC source, said dimming system comprising: a switch for connecting in series with said ballast, said switch adapted to turn on and off at a high frequency during a notch period within each half-cycle of current supplied to said ballast by said AC source and adapted to turn on during the portions of each half-cycle outside of said notch period; a high voltage integrated circuit connected to said switch including a driver circuit for connecting to the control electrode of said switch, detector means for generating current zero signals, and current means for generating a current signal having a magnitude proportional to the instantaneous current flowing in said switch; a matrix chip connected to said high voltage integrated circuit including integrating means for integrating said current signal, notch timing means for generating said notch period, pulse means for generating pulses at said high frequency during said notch period, and logic gate means for combining the outputs of said notch timing means and said pulse means to generate a gate signal for coupling to said drive circuit; and a microprocessor connected to said matrix chip for controlling said matrix chip in accordance with a desired light level of said fluorescent lamps.

Claim 43

The dimming system of claim 37 wherein said switch is comprised of an IGT.

Claim 44

The dimming system of claim 37 further comprising clamping means adapted to be connected in parallel with said ballast for clamping the voltage across said ballast to a predetermined value.