US4659946A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory gate for error sampler
Assignee: Tektronix Inc
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Filing: 1986-04-14
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Granted: 1987-04-21
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Expires: 2006-04-14
Abstract
Abstract A memory gate for an error sampler comprises a memory capacitor having one terminal connected to a reference potential level. A current steering network has an input terminal at which it receives signal current and also has an output terminal connected to the other terminal of the memory capacitor. The current steering network either directs current received at its input terminal to its output terminal or diverts the current from the output terminal, depending on the relationship between the potential at a control terminal of the current steering network and the potential at the output terminal of the current steering network. The potential at the control terminal is biased to follow the potential at the output terminal of the current steering network, and therefore the amount by which the potential at the control terminal must be changed in order to change the state of the current steering network is independent of the voltage on the memory capacitor. A switch circuit is responsive to a gate control signal to place the current steering network in one or other of its states.
Inventors
- 👤 Agoston Agoston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:21
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/74
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
208 words
A memory gate for an error sampler, comprising a memory capacitor having a first terminal connected to a reference potential level and also having a second terminal, and current steering means having an input terminal for receiving current, an output terminal connected to the second terminal of the capacitor, and a control terminal, said current steering means having a first state in which the potential at the control terminal of the current steering means bears a first predetermined relationship with the potential at the output terminal and current received at the input terminal is delivered to the output terminal, and a second state in which the potential at the control terminal of the current steering means bears a second predetermined relationship to the potential at the output terminal and current received at the input terminal is diverted from the output terminal, and the memory gate also comprising follower means to bias the potential at the control terminal of the current steering means towards said first predetermined relationship with the potential at the output terminal of the current steering means, and switch means responsive to a gate control signal to place the potential at the control terminal in said second predetermined relationship with the potential at said output terminal.
Claim 2
Dependent Claim
208 words
A memory gate for an error sampler, comprising a memory capacitor having a first terminal connected to a reference potential level and also having a second terminal, and current steering means having an input terminal for receiving current, an output terminal connected to the second terminal of the capacitor, and a control terminal, said current steering means having a first state in which the potential at the control terminal of the current steering means bears a first predetermined relationship with the potential at the output terminal and current received at the input terminal is delivered to the output terminal, and a second state in which the potential at the control terminal of the current steering means bears a second predetermined relationship to the potential at the output terminal and current received at the input terminal is diverted from the output terminal, and the memory gate also comprising follower means to bias the potential at the control terminal of the current steering means towards said first predetermined relationship with the potential at the output terminal of the current steering means, and switch means responsive to a gate control signal to place the potential at the control terminal in said second predetermined relationship with the potential at said output terminal.
Claim 3
Dependent Claim
96 words
A memory gate according to claim 1, wherein the current steering means comprise first and second diodes connected in series between the input terminal of the current steering means and the output terminal thereof, a transistor of which the base constitutes the control terminal of the current steering means, and a third diode connected between the input terminal of the current steering means and the emitter of the transistor, so that when the transistor receives base current the current received at the input terminal is diverted through the third diode to the collector of the transistor.
Claim 4
Dependent Claim
82 words
A memory gate according to claim 2, wherein the switch means comprise a second transistor having its base connected to recive the gate control signal and having its collector and emitter coupled to reference potential levels that are positive and negative respectively relative to the first-mentioned reference potential level, and a third transitor having its base, emitter and collector coupled respectively to the collector of the second transistor, the positive reference potential level, and the control terminal of the current steering means.
Claim 5
Dependent Claim
98 words
A memory gate according to claim 1, wherein the follower means comprise an amplifier having an input terminal connected to the second terminal of the memory capacitor and having an output terminal of which the potential follows the potential at the input terminal, a diode having its anode connected to the output terminal of the amplifier, and first and second resistors connecting the cathode of the diode to the control terminal of the current steering means and to a second reference potential level respectively, said second reference potential level being negative relative to the first-mentioned reference potential level.
References Cited (Backward Citations)
US3309618A
Cited
US3480795A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-20 | 1990-10-20 | 1991-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-20 | 1994-10-20 | 1995-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-20 | 1998-10-20 | 1999-04-21 | $7700.00 | Window Closed / Lapsed |