Serial minimum shift-keyed modem

Claim 2

Serial minimum shift keyed divide-by-two (SMSK/2) modem, wherein said SMSK/2 modem is defined as dividing an incoming serial bit stream data signal by two and transmitting and receiving a modulated minimum shift keyed (MSK) serial signal, said SMSK/2 modem comprising: SMSK/2 modulator means having at least three phase changes possible per bit period; and SMSK/2 demodulator means for demodulating said modulated signal.

Claim 3

The SMSK/2 device of claim 1 wherein said SMSK/2 modulator means comprises: a divide-by-2 circuit having an input and an output said input being coupled to receive said data signal; a first logic gate having a first input, a second input and an output, said first input being coupled to receive said data signal and said second input being coupled to said output of said divide-by-2 circuit; an I/Q modulator having a first input, a second input, a third input and an output, said first input being coupled to said output of said first logic gate, said second input being coupled to said output of said divide-by-2 circuit, said third input being coupled to receive a reference signal and said I/Q modulator providing a signal having phase changes; and phase trajectory converter means for converting said phase changes of said signal provided from said I/Q modulator, said phase trajectory converter means having an input and an output, said input being coupled to said output of said I/Q modulator and said output being coupled to an output of said SMSK/2 modulator means.

Claim 4

The SMSK/2 device of claim 2 wherein said phase trajectory converter means comprises: a first bandpass filter having an input and an output said input being coupled to said output of said I/Q modulator; a first hard limiter having an input and an output, said input being coupled to said output of said first bandpass filter; a second bandpass filter having an input and an output said input being coupled to said output of said first hard limiter; a second hard limiter having an input and an output, said input being coupled to said output of said second bandpass filter; and a third bandpass filter having an input and an output, said input being coupled to said output of said second hard limiter and said output being coupled to said output of said SMSK/2 modulator.

Claim 5

The SMSK/2 device of claim 3 wherein said SMSK/2 demodulator comprises; an I/Q phase detector having a first input, a second input, a first output and a second output said first input being coupled to receive a signal from said output of said SMSK/2 modulator; a matched filter having a first input, a second input, a first output, and a second output, said first input being coupled to said first output of said I/Q phase detector and said second input being coupled to said second output of said I/Q phase detector; a hard limiter having an input and an output, said input being coupled to said first output of said matched filter; a mixer having a first input, a second input and an output said first input being coupled to said output of said hard limiter and said second input being coupled to said second output of said matched filter; a loop filter having an input and an output, said input being coupled to said output of said mixer; a voltage controlled oscillator having an input and an output said input being coupled to said output of said loop filter and said output being coupled to said second input of said I/Q phase detector; a threshold detector having a first input, a second input and an output, said first input being coupled to said output of said hard limiter and said second input being coupled to receive a data clock signal; a flip flop having an input and an output said input being coupled to said output of said threshold detector; and a second logic gate having a first input, a second input and an output said first input being coupled to said output of said threshold detector, said second input being coupled to said output of said flip flop and said output being coupled to an output of said SMSK/2 demodulator.

Claim 6

The SMSK/2 device of claim 1 wherein said SMSK/2 modulator means comprises: a divide-by-2 circuit having an input and an output said input being coupled to receive said data signal; a first logic gate having a first input, a second input and an output, said first input being coupled to receive said data signal and said second input being coupled to said output of said divide-by-2 circuit; data coder/phase modulator means for creating phase changes per bit time, said data coder/phase modulator having a first input, a second input, a third input and an output, said first input being coupled to said output of said first logic gate, said second input being coupled to said output of said divide-by-2 circuit and said third input being coupled to receive a reference signal; a second bandpass filter having an input and an output, said input being coupled to said output of said data coder/phase modulator means; a second hard limiter having an input and an output, said input being coupled to said output of said second bandpass filter; and a third bandpass filter having an input and an output said input being coupled to said output of said second hard limiter and said output being coupled to said output of said SMSK/2 modulator.

Claim 7

The SMSK/2 device of claim 5 wherein said data coder/phase modulator means comprises: an I/Q modulator having a first input, a second input, a third input and an output, said first input being coupled to said first input of said data coder/phase modulator, said second input being coupled to said second input of said data coder/phase modulator and said third input being coupled to said third input of said data coder/phase modulator; a first bandpass filter having an input and an output, said input being coupled to said output of said I/Q modulator; and a first hard limiter having an input and an output, said input being coupled to said output of said first bandpass filter and said output being coupled to said output of said data coder/phase modulator means.

Claim 8

The SMSK/2 device of claim 6 wherein said SMSK/2 demodulator comprises: an I/Q phase detector having a first input, a second input, a first output and a second output said first input being coupled to receive a signal from said output of said SMSK/2 modulator; a matched filter having a first input, a second input, a first output, and a second output, said first input being coupled to said first output of said I/Q phase detector and said second input being coupled to said second output of said I/Q phase detector; a hard limiter having an input and an output, said input being coupled to said first output of said matched filter; a mixer having a first input, a second input and an output said first input being coupled to said output of said hard limiter and said second input being coupled to said second output of said matched filter; a loop filter having an input and an output, said input being coupled to said output of said mixer; a voltage controlled oscillator having an input and an output said input being coupled to said output of said loop filter and said output being coupled to said second input of said I/Q phase detector; a threshold detector having a first input, a second input and an output, said first input being coupled to said output of said hard limiter and said second input being coupled to receive a data clock signal; a flip flop having an input and an output said input being coupled to said output of said threshold detector; and a second logic gate having a first input, a second input and an output said first input being coupled to said output of said threshold detector, said second input being coupled to said output of said flip flop and said output being coupled to an output of said SMSK/N demodulator.

Claim 9

The SMSK/2 device of claim 7 wherein said divide-by-2 circuit is comprised of a flip flop circuit.

Claim 10

The SMSK/2 device of claim 8 wherein said first and second logic gates are comprised of dual input exclusive OR gates.

Claim 13

The method of claim 10 wherein said smoothing step comprises the steps of: filtering said modulated signal with a first bandpass filter; limiting said signal with a first hard limiter; filtering said signal with a second bandpass filter; limiting said signal with a second hard limiter; and filtering said signal with a third bandpass filter producing a modulated signal.

Claim 14

The method of claim 11 further comprising the step of demodulating said modulated signal.

Claim 15

The method of claim 12 wherein said step of demodulating comprises the steps of: detecting said signal with an I/Q detector; filtering said signal with a matched filter; limiting said signal using a hard limiter; detecting said signal with a threshold detector; and timing the output of said signal using a flip flop in series with a logic gate.

Claim 16

Serial Minimum shift keyed divide-by-two (SMSK/2) modem having at least three phase changes, comprising: a divide-by-2 circuit having an input and an output, said input being coupled to receive a data signal; a first logic gate having a first input, a second input and an output, said first input being coupled to receive said data signal and said second input being coupled to said output of said divide-by-2 circuit; an I/Q modulator having a first input, a second input, a third input and an output, said first input being coupled to said output of said first logic gate, said second input being coupled to said output of said divide-by-2 circuit and said third input being coupled to receive a reference signal; a first bandpass filter having an input and an output said input being coupled to said output of said I/Q modulator; a first hard limiter having an input and an output said input being coupled to said output of said first bandpass filter; a second bandpass filter having an input and an output said input being coupled to said output of said first hard limiter; a second hard limiter having an input and an output, said input being coupled to said output of said second bandpass filter; a third bandpass filter having an input and an output, said input being coupled to said output of said second hard limiter; transmitting means for transmitting a signal received from said third bandpass filter, said transmitting means having an input being coupled to said output of said third bandpass filter; receiving means for receiving said signal from said transmitting means, said receiving means having an output; an I/Q phase detector having a first input, a second input, a first output and a second output, said first input being coupled to said output of said receiving means; a matched filter having a first input, a second input, a first output and a second output, said first input being coupled to said first output of said I/Q phase detector and said second input being coupled to said second output of said I/Q phase detector; a third hard limiter having an input and an output, said input being coupled to said first output of said matched filter; a mixer having a first input, a second input and an output, said first input being coupled to said output of said hard limiter and said second input being coupled to said second output of said matched filter; a loop filter having an input and an output, said input being coupled to said output of said mixer; a voltage controlled oscillator having an input and an output, said input being coupled to said output of said loop filter and said output being coupled to said second input of said I/Q phase detector; a threshold detector having a first input, a second input and an output, said first input being coupled to said output of said third hard limiter and said second input being coupled to receive a data clock signal; a flip flop having an input and an output said input being coupled to said output of said threshold detector; and a second logic gate having a first input, a second input and an output, said first input being coupled to said output of said threshold detector, said second input being coupled to said output of said flip flop and said output being coupled to an output of said SMSK/2 modem.

Claim 17

Serial Minimum shift keyed divide-by-two (SMSK/2) modem having at least three phase changes, comprising: a divide-by-2 circuit having an input and an output, said input being coupled to receive a data signal; a first logic gate having a first input, a second input and an output, said first input being coupled to receive said data signal and said second input being coupled to said output of said divide-by-2 circuit; an I/Q modulator having a first input, a second input, a third input and an output, said first input being coupled to said output of said first logic gate, said second input being coupled to said output of said divide-by-2 circuit and said third input being coupled to receive a reference signal; a first bandpass filter having an input and an output said input being coupled to said output of said I/Q modulator; a first hard limiter having an input and an output said input being coupled to said output of said first bandpass filter; a second bandpass filter having an input and an output said input being coupled to said output of said first hard limiter; a second hard limiter having an input and an output, said input being coupled to said output of said second bandpass filter; a third bandpass filter having an input and an output, said input being coupled to said output of said second hard limiter; transmitting means for transmitting a signal received from said third bandpass filter, said transmitting means having an input being coupled to said output of said third bandpass filter; receiving means for receiving said signal from said transmitting means, said receiving means having an output; an I/Q phase detector having a first input, a second input, a first output and a second output, said first input being coupled to said output of said receiving means; a matched filter having a first input, a second input, a first output and a second output, said first input being coupled to said first output of said I/Q phase detector and said second input being coupled to said second output of said I/Q phase detector; a third hard limiter having an input and an output, said input being coupled to said first output of said matched filter; a mixer having a first input, a second input and an output, said first input being coupled to said output of said hard limiter and said second input being coupled to said second output of said matched filter; a loop filter having an input and an output, said input being coupled to said output of said mixer; a voltage controlled oscillator having an input and an output, said input being coupled to said output of said loop filter and said output being coupled to said second input of said I/Q phase detector; a threshold detector having a first input, a second input and an output, said first input being coupled to said output of said third hard limiter and said second input being coupled to receive a data clock signal; a flip flop having an input and an output said input being coupled to said output of said threshold detector; and a second logic gate having a first input, a second input and an output, said first input being coupled to said output of said threshold detector, said second input being coupled to said output of said flip flop and said output being coupled to an output of said SMSK/2 modem.

Claim 18

The SMSK/2 device of claim 15 wherein said first and second logic gates are comprised of dual input exclusive OR gates.