Semiconductor memory device providing a selection circuit change-over arrangement

Claim 1

A semiconductor memory device including: (a) a plurality of memory elements each of which has a first terminal and a second terminal, and each of which is capable of semi-permanently changing its impedance from a given value to another value; (b) a selecting circuit which receives address signals and which selects a memory element designated by the address signals out of said plurality of memory elements; (c) a third terminal which is supplied with a writing current; (d) a fourth terminal which is supplied with a writing signal that is to be written on a selected one of said plurality memory elements; and (e) a control circuit having a writing circuit which, when the writing current is supplied to said third terminal, supplies the writing current from said third terminal to the first terminal of the memory element that is selected by the selecting circuit out of said plurality of said plurality of memory elements, and which further supplies a current in accordance with the writing signal sent from said fourth terminal to the second terminal of said selected memory element so that the impedance of the selected memory element is set to a value which complies with the writing signal, wherein said selecting circuit comprises a first selecting circuit and a second selecting circuit, wherein said first selecting circuit receives said address signals and selects said selected memory element in the reading operation when a first level signal of said writing current is supplied to said third terminal, and wherein said second selecting cirucit receives said address signals and selects said selected memory element in the writing operation when a second level signal of said writing current is supplied to said third terminal.