Chip carrier connector and method of making same

Claim 1

A chip carrier connector, comprising: an array of parallel spaced electrical terminal posts selectively positioned and having upper sections and bottom sections, said upper sections adapted to be electrically connected with respective conductive areas of a ceramic chip carrier, and said bottom sections to be inserted into respective holes in a printed circuit board for electrical connection with respective circuit paths thereof; a dielectric frame molded to said terminal posts proximate said upper sections thereof; a ceramic chip carrier having conductive areas within which said upper sections of said terminal posts are secured and electrically connected and adapted to receive a circuit chip therein and having circuit paths extending from said circuit chip to said conductive areas; and said connector including a dielectric aligning means comprising a dielectric flexible substrate containing no preformed apertures forced over said terminal posts between said upper sections and bottom sections thereof prior to said securing of said chip carrier to said terminal posts, said dielectric aligning means adapted to be movable along said bottom sections of said terminal posts to a position adjacent the ends thereof to align said bottom sections with said respective holes in said printed circuit board for insertion thereinto.

Claim 5

A method of making an electronic component package having an array of parallel spaced electrical terminal posts with bottom sections alignable for insertion into respective holes of a printed circuit board without pre-insertion into holes of an alignment device, comprising the steps of: arranging an array of electrical terminal posts in a selected arrangement such that said posts are spaced and parallel; molding a dielectric frame to said terminal posts proximate upper sections thereof such that after completion of said package said dielectric frame is movable along bottom sections of said terminal posts to a position adjacent the ends thereof thereby aligning said ends for insertion into respective holes in a printed circuit board; and securing to said upper sections of said terminal posts an electronic component having circuit paths electrically connected to respective said terminal posts.

Claim 6

A method of making an electronic component package having an array of parallel spaced electrical terminal posts with bottom sections alignable for insertion into respective holes of a printed circuit board without pre-insertion into holes of an alignment device, comprising the steps of: arranging an array of electrical terminal posts in a selected arrangement such that said posts are spaced and parallel; molding a dielectric frame to said terminal posts proximate upper sections thereof such that after completion of said package said dielectric frame is movable along bottom sections of said terminal posts to a position adjacent the ends thereof thereby aligning said ends for insertion into respective holes in a printed circuit board; and securing to said upper sections of said terminal posts an electronic component having circuit paths electrically connected to respective said terminal posts.