US4654780A
Expired / Lapsed
US
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Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
Assignee: Unisys Corp
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Filing: 1984-06-05
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Granted: 1987-03-31
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Expires: 2004-06-05
Abstract
Abstract A parallel register-transfer mechanism has been disclosed above for use in the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expression is reduced through a series of transformations until a result is obtained. A register file is provided with several crossbar networks interconnecting the various registers in the file for simultaneous transfer of their contents.
Inventors
- 👤 Gary L. Logsdon
- 👤 Mark R. Scheevel
- 👤 Brent C. Bolton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032; G06F9/30072; G06F9/30098; G06F9/30141; G06F9/44; G06F9/448; G06F9/4494
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
70 words
In a processor for manipulating data, a register file, said register file comprising: a plurality of registers for storing fields of information; interconnection means coupling said registers together for parallel transfer of fields of information from some of said registers to other of said registers; and said interconnection means includes a crossbar network for connecting each of the said registers to other of said registers for said parallel information transfer.
Claim 2
Dependent Claim
70 words
In a processor for manipulating data, a register file, said register file comprising: a plurality of registers for storing fields of information; interconnection means coupling said registers together for parallel transfer of fields of information from some of said registers to other of said registers; and said interconnection means includes a crossbar network for connecting each of the said registers to other of said registers for said parallel information transfer.
Claim 3
Dependent Claim
48 words
A register file according to claim 1 wherein: said crossbar network is a composite of a plurality of crossbar networks for coupling different fields of such registers to other fields of the other of said registers for parallel transfer of certain of said fields to said other registers.
Claim 4
Dependent Claim
140 words
In a reduction processing system having storage means for receiving two-cell nodes representing binary directed graphs employing a variable-free applicative language code, one of such cells in some of each nodes containing a storage address of another node, another of said cells in some of each nodes containing a code representing a functional argument and another of said cells in some of each nodes containing a variable-free operator code specifying a function substitution, said system including a register file, said register file comprising: a plurality of registers for storing fields of information: interconnection means coupling said registers together for parallel transfer of fields of information from some of said registers to other of said registers; and said interconnection means includes a crossbar network for connecting each of the said registers to other of said registers for said parallel information transfer.
Claim 5
Dependent Claim
140 words
In a reduction processing system having storage means for receiving two-cell nodes representing binary directed graphs employing a variable-free applicative language code, one of such cells in some of each nodes containing a storage address of another node, another of said cells in some of each nodes containing a code representing a functional argument and another of said cells in some of each nodes containing a variable-free operator code specifying a function substitution, said system including a register file, said register file comprising: a plurality of registers for storing fields of information: interconnection means coupling said registers together for parallel transfer of fields of information from some of said registers to other of said registers; and said interconnection means includes a crossbar network for connecting each of the said registers to other of said registers for said parallel information transfer.
Claim 6
Dependent Claim
38 words
A register file according to claim 3 wherein: said plurality of registers includes registers containing information specifying a type of node, registers containing the left cell of a node and registers containing the right cell of a node.
Claim 7
Dependent Claim
50 words
A register file according to claim 4 wherein: said crossbar network is a composite of a plurality of crossbar networks for coupling different fields of said registers to other fields of other of said registers for parallel transfer of certain of said fields to other fields of said other registers.
Claim 8
Dependent Claim
141 words
In a reduction processing system having storage means for receiving two-cell nodes representing binary directed graphs supplying a variable-free applicative language code, one of such cells in some of each nodes containing a storage address of another node, another of said cells in some of each nodes containing a code representing a functional argument and another of such cells in some of each nodes containing a variable-free operator code specifying a function substitution, said system comprising: a register file including a plurality of registers for storing fields of information and interconnection means coupling said registers together for parallel transfer of fields from some of said registers to other of said registers; and a plurality of buffer registers coupled to said register file for storing nodes of portions of the graph being reduced which nodes do not reside in said register file.
Claim 9
Dependent Claim
141 words
In a reduction processing system having storage means for receiving two-cell nodes representing binary directed graphs supplying a variable-free applicative language code, one of such cells in some of each nodes containing a storage address of another node, another of said cells in some of each nodes containing a code representing a functional argument and another of such cells in some of each nodes containing a variable-free operator code specifying a function substitution, said system comprising: a register file including a plurality of registers for storing fields of information and interconnection means coupling said registers together for parallel transfer of fields from some of said registers to other of said registers; and a plurality of buffer registers coupled to said register file for storing nodes of portions of the graph being reduced which nodes do not reside in said register file.
Claim 10
Dependent Claim
35 words
A system according to claim 6 wherein: said buffer registers are arranged in a last in-first out connection to form a stack with input and output always being from the top register of said stack.
Claim 11
Dependent Claim
45 words
A system according to claim 6 wherein: said interconnection means includes a crossbar network for connecting each of said registers of said register file to other of said registers of said register file and to the top of the stack register for parallel information transfer.
References Cited (Backward Citations)
US3710348A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-30 | 1990-09-29 | 1991-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-30 | 1994-09-29 | 1995-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-30 | 1998-09-29 | 1999-03-31 | $7700.00 | Window Closed / Lapsed |