US4652902A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power semiconductor device
Assignee: Mitsubishi Electric Corp
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Filing: 1984-12-21
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Granted: 1987-03-24
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Expires: 2004-12-21
Abstract
Abstract The present invention comprises a power semiconductor device in which a bipolar transistor and a diode are formed in antiparallel in a semiconductor chip with an emitter electrode (21) on one surface of the transistor (16) serving also as an anode electrode of the diode and a collector electrode (23) on another surface of the transistor serving also as a cathode electrode of the diode. A plurality of emitter lead wires (24) of the power transistor serving also as anode lead wires of the diode are connected in the anode region of the diode. Thus, electric current is made to flow from the anode region of the diode to the cathode thereof if a short circuit occurs, so that the lead wires can be prevented from being melted by large current.
Inventors
- 👤 Ikunori Takata
- 👤 Takayuki Kitamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:03
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/003; H10; H10D; H10D84/00; H10D84/60; H10D84/641; H10D84/642; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/484; H10W44/00; H10W44/401; H10W90/00; H10W72/00; H10W72/50; H10W72/531; H10W72/5363; H10W72/5366; H10W72/541; H10W72/547; H10W72/5475; H10W72/551; H10W72/552; H10W72/5524; H10W72/59; H10W72/90; H10W72/921; H10W72/926; H10W72/931; H10W72/932; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
113 words
A power semiconductor device in which a power semiconductor active device and a diode are formed in antiparallel in a semiconductor chip having a one surface and an other surface, comprising: a main electrode formed on said one surface of said semiconductor chip, said main electrode functioning as a first electrode of both said device and said diode, a common main electrode formed on said other surface of said semiconductor chip to be opposed to said main electrode, said common main electrode serving as a second electrode of both said power semiconductor active device and said diode, and a plurality of outgoing lead wires connected to a diode region of said main electrode.
Claim 2
Dependent Claim
113 words
A power semiconductor device in which a power semiconductor active device and a diode are formed in antiparallel in a semiconductor chip having a one surface and an other surface, comprising: a main electrode formed on said one surface of said semiconductor chip, said main electrode functioning as a first electrode of both said device and said diode, a common main electrode formed on said other surface of said semiconductor chip to be opposed to said main electrode, said common main electrode serving as a second electrode of both said power semiconductor active device and said diode, and a plurality of outgoing lead wires connected to a diode region of said main electrode.
Claim 3
Dependent Claim
43 words
A power semiconductor device in accordance with claim 1, wherein said bipolar semiconductor active device is a power transistor, said first electrode of said power semiconductor active device is an emitter electrode, and said first electrode of said diode is an anode electrode.
Claim 4
Dependent Claim
45 words
A power semiconductor device in accordance with claim 1, wherein said power semiconductor active device is a power field effect transistor, said first electrode of said power semiconductor active device is a source electrode and said first electrode of said diode is an anode electrode.
Claim 5
Dependent Claim
41 words
A power semiconductor device in accordance with claim 1, wherein said power semiconductor device is a thyristor, said first electrode of said power semiconductor active device is a cathode electrode, and said first electrode of said diode is an anode electrode.
Claim 6
Dependent Claim
17 words
A power semiconductor device in accordance with claim 4, wherein said thyristor is a gate turn-off thyristor.
References Cited (Backward Citations)
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JPS56104700A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-23 | 1990-09-22 | 1991-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-23 | 1994-09-22 | 1995-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-23 | 1998-09-22 | 1999-03-24 | $7700.00 | Window Closed / Lapsed |