Access control for a plurality of modules to a common bus

Claim 1

In a system having a plurality of modules connected in parallel to a common bus for receiving data from the common bus and transmitting data to the common bus, a priority system for controlling the sequence in which requests made by said modules for access to the common bus is granted, comprising: a bus busy line, capable of being maintained at a first predetermined voltage if the common bus is not busy, and at a second predetermined voltage if the common bus is busy; a control and timing logic unit in each of said modules for sensing the voltage on said bus busy line, permitting access to the bus if said bus busy line is at said first predetermined voltage and inhibiting access to the common bus if said bus busy line is at said second predetermined voltage; a resistance in each of said modules; means for switching the direction of current flow through each resistance in each of said modules; a grant line for connecting, in series, all of said resistances in each of said modules, and capable of further connections at both ends of said grant line beyond said resistances; means suitable for energizing both ends of said grant line by constant current sources; means for preventing saturation of said constant current sources; and means included in each of said modules for permitting access by each module to the common bus only when the current flow through the module's included resistance is in a predetermined direction.