US4651269A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current flow reversing circuit
Assignee: Toshiba Corp
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Filing: 1985-05-02
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Granted: 1987-03-17
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Expires: 2005-05-02
Abstract
Abstract There is disclosed a circuit for reversing an electric current flow comprising a motor, a circuit formed of a first transistor at a power source V CC side and a third transistor at the ground side which are connected in series, a circuit formed of a second transistor at the power source V CC side and a fourth transistor at the ground side which are connected in series, the junction of the first and third transistors being connected to one terminal of the motor and the junction of the second and fourth transistors being connected to the other terminal of the motor, and a pulse generator for producing an output signal which delays the turn-on timing of the third or fourth transistor until the state of the first or second transistor has been changed from an on-state to an off-state.
Inventors
- 👤 Ken Matsumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:34
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/38; H02P; H02P7/00; H02P7/03; H02P7/04
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
225 words
A circuit for reversing the flow of electric current comprising: a load driven by current and having first and second terminals to which the current is applied; first and second potential sources; first and second transistors each having collector-emitter paths respectively connected between the first potential source and said first terminal and between said first potential source and said second terminal; third and fourth transistors each having collector-emitter paths respectively connected between said first terminal and said second potential source and between said second terminal and said second potential source; said first and fourth transistors forming a first circuit for directing current flow through said load in one direction, and said second and third transistors forming a second circuit for directing current flow through said load in the opposite direction; bias means for reversing the biasing state of each of said first circuit and said second circuit, thereby to cause said circuits to operate alternately and reverse the flow of the current flowing through said load; and pulse generating means for applying first and second control pulses to, respectively, said third and fourth transistors to delay the turning-on of said third transistor until said first transistor is turned off during operation of said second circuit, and the turning-on of said fourth transistor until said second transistor is turned off during operation of said first circuit.
Claim 2
Dependent Claim
225 words
A circuit for reversing the flow of electric current comprising: a load driven by current and having first and second terminals to which the current is applied; first and second potential sources; first and second transistors each having collector-emitter paths respectively connected between the first potential source and said first terminal and between said first potential source and said second terminal; third and fourth transistors each having collector-emitter paths respectively connected between said first terminal and said second potential source and between said second terminal and said second potential source; said first and fourth transistors forming a first circuit for directing current flow through said load in one direction, and said second and third transistors forming a second circuit for directing current flow through said load in the opposite direction; bias means for reversing the biasing state of each of said first circuit and said second circuit, thereby to cause said circuits to operate alternately and reverse the flow of the current flowing through said load; and pulse generating means for applying first and second control pulses to, respectively, said third and fourth transistors to delay the turning-on of said third transistor until said first transistor is turned off during operation of said second circuit, and the turning-on of said fourth transistor until said second transistor is turned off during operation of said first circuit.
Claim 3
Dependent Claim
78 words
A circuit for reversing the flow of electric current according to claim 1, wherein said bias means comprises a first bias circuit for biasing said first transistor, a second bias circuit for biasing said second transistor, a third bias circuit for biasing said third transistor and a fourth bias circuit for biasing said fourth transistor, the third bias circuit being supplied with said first control pulse and the fourth bias circuit being supplied with said second control pulse.
Claim 4
Dependent Claim
148 words
A circuit for reversing the flow of electric current according to claim 1, comprising a control circuit responsive to control input pulses and having outputs connected to said bias means for controlling the bias applied to said first and second circuits, and wherein said pulse generating means comprises a first pulse generating circuit including an inverter for inverting said control input pulse, a first capacitor which is charged or discharged in synchronism with the leading edge and the trailing edge of a pulse outputted from the said inverter and a first voltage comparator for comparing the voltage across said capacitor with a reference voltage, and a second pulse generating circuit including a capacitor which is charged and discharged in synchronism with the leading and trailing edges of said control input pulse and a second voltage comparator for comparing a voltage across said second capacitor with the reference voltage.
Claim 5
Dependent Claim
65 words
A circuit for reversing an electric current flow according to claim 3, wherein said first pulse generating circuit further comprises a circuit for logically processing the output signal of said first comparator and the output pulse from said inverter circuit, and said second pulse generating circuit further comprises a circuit for logically processing the output signal from said second comparator and said control input pulse.
Claim 6
Dependent Claim
46 words
A circuit for reversing an electric current flow according to claim 3, further comprising a circuit for logically processing the output signal of said first comparator in said first pulse generating circuit, and the output signal of said second comparator of said second pulse generating circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-16 | 1990-09-15 | 1991-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-16 | 1994-09-15 | 1995-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-16 | 1998-09-15 | 1999-03-17 | $7700.00 | Window Closed / Lapsed |