US4651252A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor fault tolerance method and apparatus
Assignee: Eaton Corp
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Filing: 1985-03-29
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Granted: 1987-03-17
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Expires: 2005-03-29
Abstract
Abstract A power transistor control circuit for controlling the bias input to the power transducer. During normal operations two switching transistors bias the base input to a power transistor positively and negatively to turn the power transistor on and off. By back biasing a conducting transistor, however, the blocking voltage capability of the transistor is diminished. To maintain blocking voltage at a maximum, the present circuit senses overcurrent conditions indicating a problem condition exists and turns off the power transistor by neutrally biasing a base input. Preferably, both switching transistors used to bias the base input during normal operation of the transistor are rendered nonconductive to accomplish this neutral biasing.
Inventors
- 👤 Thomas E. Babinski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:49
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/082; H03K17/0826
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
147 words
A method in controlling the operation of a power transistor by adjusting a bias voltage across a base-emitter junction of said power transistor comprising the steps of: providing positive and negative biasing potentials for controlling a bias potential at a base input to said power transistor; forward and reverse biasing said base input to turn on and off said power transistor during normal transistor operation by selectively coupling one of said positive and negative biasing potentials to said base input; monitoring operation of said power transistor to sense a failure condition of said power transistor; and neutrally biasing said base input in the event a failure condition is sensed to turn off said power transistor without reverse biasing said base-emitter junction to maximize a voltage blocking capability of said transistor as charge carriers are swept from the base of said transistor as part of a collector current.
Claim 2
Independent Claim
147 words
A method in controlling the operation of a power transistor by adjusting a bias voltage across a base-emitter junction of said power transistor comprising the steps of: providing positive and negative biasing potentials for controlling a bias potential at a base input to said power transistor; forward and reverse biasing said base input to turn on and off said power transistor during normal transistor operation by selectively coupling one of said positive and negative biasing potentials to said base input; monitoring operation of said power transistor to sense a failure condition of said power transistor; and neutrally biasing said base input in the event a failure condition is sensed to turn off said power transistor without reverse biasing said base-emitter junction to maximize a voltage blocking capability of said transistor as charge carriers are swept from the base of said transistor as part of a collector current.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein the monitoring step is performed by monitoring a current flow through the transistor.
Claim 4
Dependent Claim
18 words
The method of claim 1 wherein the monitoring step is performed by monitoring a voltage across the transistor.
Claim 5
Dependent Claim
113 words
Circuitry to control conduction of a power transistor comprising: positive and negative power supply means for applying positive and negative potentials to a base-emitter junction of said power transistor; first and second switching means for coupling one of said positive and negative power supply means to a base input of said transistor to bias said transistor to conduct and to stop conducting; sensing means for sensing a potential failure condition in said transistor; and control means coupled to said sensing means to deactive the first and second switching means and neutrally bias said base input at a voltage between said positive and negative bias potentials in response to a sensed potential failture condition.
Claim 6
Dependent Claim
113 words
Circuitry to control conduction of a power transistor comprising: positive and negative power supply means for applying positive and negative potentials to a base-emitter junction of said power transistor; first and second switching means for coupling one of said positive and negative power supply means to a base input of said transistor to bias said transistor to conduct and to stop conducting; sensing means for sensing a potential failure condition in said transistor; and control means coupled to said sensing means to deactive the first and second switching means and neutrally bias said base input at a voltage between said positive and negative bias potentials in response to a sensed potential failture condition.
Claim 7
Dependent Claim
49 words
The circuitry of claim 4 wherein the first and second switching means comprises first and second switching transistors to apply positive and negative control voltages to the base input and the control means renders both said switching transistors nonconductive to neutrally bias said base input of said power transistor.
Claim 8
Dependent Claim
31 words
The circuitry of claim 4 where the sensing means comprises a current sensor for sensing current flow through the transistor and deactivating said switching means if an overcurrent condition is sensed.
Claim 9
Dependent Claim
30 words
The circuitry of claim 4 wherein the sensing means comprises a voltage sensor for monitoring operation of the transistor and deactivating the switching means if an overvoltage condition is sensed.
Claim 10
Dependent Claim
173 words
Apparatus comprising: a power transistor having a base control input for controlling conduction of said transistor by contolling an emitter base junction voltage; a PNP switching transistor having a collector electrically coupled to the base of said power transistor and an emitter coupled to a positive voltage source so that when said PNP switching transistor conducts a positive bias signal is coupled to the base of said power transistor to turn on said power transistor; a NPN switching transistor having a collector electrically coupled to the base of said power transistor and an emitter coupled to a negative voltage source so that when said NPN switching transistor conducts, a negative reverse biasing signal is coupled to the base of the power transistor to turn off said power transistor; and failure sensing means coupled to the power transistor to sense a failure condition in said power transistor and render both said switching transistors nonconductive to apply a neutral bias to the base control input of the power transistor and render said power transistor nonconductive.
Claim 11
Dependent Claim
173 words
Apparatus comprising: a power transistor having a base control input for controlling conduction of said transistor by contolling an emitter base junction voltage; a PNP switching transistor having a collector electrically coupled to the base of said power transistor and an emitter coupled to a positive voltage source so that when said PNP switching transistor conducts a positive bias signal is coupled to the base of said power transistor to turn on said power transistor; a NPN switching transistor having a collector electrically coupled to the base of said power transistor and an emitter coupled to a negative voltage source so that when said NPN switching transistor conducts, a negative reverse biasing signal is coupled to the base of the power transistor to turn off said power transistor; and failure sensing means coupled to the power transistor to sense a failure condition in said power transistor and render both said switching transistors nonconductive to apply a neutral bias to the base control input of the power transistor and render said power transistor nonconductive.
Claim 12
Dependent Claim
41 words
The apparatus of claim 8 where the failure sensing means comprises a third switching transistor to control base inputs of the first and second switching transistors and render said first and second switching transistors nonconductive if a failure condition is sensed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-16 | 1990-09-15 | 1991-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-16 | 1994-09-15 | 1995-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-16 | 1998-09-15 | 1999-03-17 | $7700.00 | Window Closed / Lapsed |