US4651132A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog to digital converter system for application to pulse code modulation
Assignee: Texas Instruments Tucson Corp
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Filing: 1985-05-20
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Granted: 1987-03-17
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Expires: 2005-05-20
Abstract
Abstract A digital audio system for high-fidelity replication of wideband audio material. The system comprises a high-speed, low-noise and low-distortion, digital-to-analog converter including means for reducing spurious switching currents in the reconstructed audio signal. Such a converter is employed in both the encoding and decoding portions of the system.
Inventors
- 👤 William J. Lillis
- 👤 Jimmy R. Naylor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:45
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/14; H03M1/145; H03M1/146
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
391 words
An analog to digital converter comprising: digital to analog converter means for providing a constructed analog signal representative of a digital input signal, said digital to analog converter means comprises most significant bit current switches and sources; least significant bit current switches and sources; a primary resistance network coupled to said least significant bit current switches and sources and to a ground terminal, said primary resistance network having an output coupled to said most significant bit current switches, each of said least significant bit current switches and sources applying current to said primary resistance network when said each least significant bit current switches and sources are in a first state; most significant bit ground buffer means coupled to said most significant bit current switches and sources for reducing a current flowing from analog ground through said most significant bit current switches; and secondary resistance network means coupled to said least significant bit current switches and sources and to said ground terminal, each of said least significant bit current switches and sources applying current to said secondary resistance means, said secondary resistance network means for providing an analog ground current contribution when said each least significant bit current switch and source is in a second state generally equal to an analog ground current contribution; compensation means coupled to selected current switches and sources for replacing at least a portion of analog ground current flowing from analog ground through said selected current switches with current flowing from a power supply when said selected current switches are in a conducting state and for substantially eliminating said analog ground current flowing through said selected current switches when said selected current switches are in a non-conducting state; generation means for generating clock pulses; register means for providing to said digital to analog converter means a parallel group of logic signals representative of the number of clock pulses generated during an interval of time, said register means including a successive approximation register; comparator means for comparing said constructed analog signal with an audio input signal, said comparator means providing a known signal during said interval determined by a relative signal strength between said constructed and said audio input signal, said parallel group of logic signals being representative of the output of said register means cleared in response to an initiate pulse at the beginning of said interval.
Claim 2
Dependent Claim
391 words
An analog to digital converter comprising: digital to analog converter means for providing a constructed analog signal representative of a digital input signal, said digital to analog converter means comprises most significant bit current switches and sources; least significant bit current switches and sources; a primary resistance network coupled to said least significant bit current switches and sources and to a ground terminal, said primary resistance network having an output coupled to said most significant bit current switches, each of said least significant bit current switches and sources applying current to said primary resistance network when said each least significant bit current switches and sources are in a first state; most significant bit ground buffer means coupled to said most significant bit current switches and sources for reducing a current flowing from analog ground through said most significant bit current switches; and secondary resistance network means coupled to said least significant bit current switches and sources and to said ground terminal, each of said least significant bit current switches and sources applying current to said secondary resistance means, said secondary resistance network means for providing an analog ground current contribution when said each least significant bit current switch and source is in a second state generally equal to an analog ground current contribution; compensation means coupled to selected current switches and sources for replacing at least a portion of analog ground current flowing from analog ground through said selected current switches with current flowing from a power supply when said selected current switches are in a conducting state and for substantially eliminating said analog ground current flowing through said selected current switches when said selected current switches are in a non-conducting state; generation means for generating clock pulses; register means for providing to said digital to analog converter means a parallel group of logic signals representative of the number of clock pulses generated during an interval of time, said register means including a successive approximation register; comparator means for comparing said constructed analog signal with an audio input signal, said comparator means providing a known signal during said interval determined by a relative signal strength between said constructed and said audio input signal, said parallel group of logic signals being representative of the output of said register means cleared in response to an initiate pulse at the beginning of said interval.
References Cited (Backward Citations)
US4292625A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-16 | 1990-09-15 | 1991-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-16 | 1994-09-15 | 1995-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-16 | 1998-09-15 | 1999-03-17 | $7700.00 | Window Closed / Lapsed |