Thermally matched mounting substrate

Claim 2

Apparatus for mounting a silicon semiconductor chip, comprising: a substrate having a thermal expansion coefficient approximating the thermal expansion coefficient silicon; said substrate comprising a graphite platelet having a conformal coating of silicon carbide; an interconnect pattern formed on said substrate; and means for adhering a chip to a select portion of said pattern, the thermal resistance of said means for adhering being minimal.

Claim 3

The apparatus of claim 1 wherein said substrate has a surface area larger than the surface area of the chip.

Claim 4

The apparatus of claim 1 wherein said interconnect pattern comprises a deposited metalized pattern on the surface of said substrate with a select area for adhering the chip to by said adhering means.

Claim 5

The apparatus of claim 1 and further comprising a topological pattern formed in said graphite platelet, said conformal coating of silicon carbide conforming to said topological pattern such that said topological pattern is reflected in the surface of said substrate.

Claim 6

The apparatus of claim 4 wherein said select portion of said topological pattern forms a well, the depth of said well being substantially the thickness of the semiconductor chip to be mounted thereupon puls the thickness of said means for adhering.

Claim 7

The apparatus of claim 1 wherein said substrate further comprises an orifice disposed therethrough with an interconnect pattern disposed on the side of said substrate opposite the side to which the chip is to be adhered, said orifice having an interconnect pattern disposed on the inner surface thereof for interconnecting both sides of said substrate.

Claim 8

The apparatus of claim 1 and further comprising insulation means disposed between said substrate and said interconnect pattern.

Claim 11

The apparatus of claim 8 and further comprising a topological pattern formed in said graphite platelet, said silicon carbide coating conforming to said topological pattern.

Claim 12

The apparatus of claim 9 wherein said topological pattern defines a well in the surface of said substrate adjacent said mounting pad such that the upper surface of the chip is disposed closer to the plane of said interconnect pattern.

Claim 13

The apparatus of claim 8 and further comprising: a metalized pattern disposed on the opposite side of said substrate from said interconnect pattern; an orifice disposed through said substrate to interconnect both sides thereof and at a selected location with respect to said interconnect pattern; said orifice formed in said graphite platelet and conformally coated with silicon carbide such that a continuous coating of silicon carbide exists between the upper surface and lower surface and the inner sides of said orifice; and a layer of metallization disposed on the innersurfaces of said orifice for interconnecting said metalized pattern on the lower surface of said substrate and a select portion of said metalized patterns.

Claim 14

The apparatus of claim 8 and further comprising a layer of insulating material disposed between said mounting pad and said substrate and also between said metalized pattern and said substrate.

Claim 15

The apparatus of claim 12 wherein said insulating layer comprises silicon dioxide.

Claim 18

The method of claim 14 and further comprising disposing an insulating layer between the mounting pad and the substrate and also between the interconnect pattern and the substrate.

Claim 19

The method of claim 14 and further comprising forming a topological pattern in the graphite platelet prior to conformally coating the substrate with the silicon carbide such that the topological pattern is reflected in the surface of the substrate.

Claim 20

The method of claim 14 and further comprising: disposing a layer of metallization on the lower surface of the substrate opposite the chip; forming an orifice in the substrate; and forming a layer of metal on the innersurfaces of the orifice to allow interconnection between the metalized undersurface of the substrate to a select portion of the interconnect pattern.

Claim 21

A substrate for mounting a silicon semiconductor chip, comprising: a body of graphite conformally coated with silicon carbide, said conformally coated body having a surface; a mounting pad disposed in a predetermined location on said surface for mounting the chip thereto; and an electrically conductive interconnect pattern disposed on said surface for allowing the chip to interface with circuitry external to said substrate.

Claim 22

A substrate for mounting a silicon semiconductor chip, comprising: a body of graphite conformally coated with silicon carbide, said conformally coated body having a surface; a mounting pad disposed in a predetermined location on said surface for mounting the chip thereto; and an electrically conductive interconnect pattern disposed on said surface for allowing the chip to interface with circuitry external to said substrate.

Claim 23

A substrate as claimed in claim 18, wherein a select portion of said surface is adapted to receive a cap to be placed over said mounting pad after said chip is mounted thereupon.

Claim 24

A substrate as claimed in claim 18, wherein said body of graphite has an orifice disposed therethrough; and wherein said conformal coating of silicon carbide covers the inner surface of said orifice.