Data acquisition

Claim 2

Apparatus comprising: means for generating a first pulse duration type signal wherein said first pulse duration type signal is periodically repeated every time period p, wherein said first pulse duration type signal is in a first state for a portion of said time period p and is in a second state for a portion of said time period p, wherein the length of time said pulse duration type signal is in said first state is representative of the value of a first variable and wherein said first pulse duration type signal is continuous; means for converting said first pulse duration type signal to a first clock signal when said first pulse duration type signal is in said first state; a first counter having a count input and an enabling input; means for supplying said first clock signal to the count input of said first counter; means for supplying a fixed period signal having a period equal to said time period p to the enabling input of said first counter, wherein the count reached by said first counter in a time period equal to said time period p is representative of the time said first pulse duration type signal is in said first state; a computer; and means for transferring the count reached by said first counter to said computer to thereby transfer to said computer the value of said first variable.

Claim 3

Apparatus in accordance with claim 1 additionally comprising; means for generating a second pulse duration type signal, wherein said second pulse duration type signal is periodically repeated every said time period p, wherein said second pulse duration type signal is in said first state for a portion of said time period p and is in said second state for a portion of said time period p, wherein the length of time that said second pulse duration type signal is in said first state is representative of the value of a second variable, wherein said second pulse duration type signal is continuous and wherein said first pulse duration type signal and said second pulse duration type signal are asynchronous; means for converting said second pulse duration type signal to a second clock signal when said second pulse duration signal is in said first state; a second counter having a count input and an enabling input; means for supplying said second clock signal to the count input of said second counter; means for supplying said fixed period signal to the enable input of said second counter, wherein the count reached by said second counter in a time period equal to said time period p is representative of the time said second pulse duration type signal is in said first state; and means for transferring the count reached by said second counter to said computer to thereby transfer to said computer the value of said second variable.

Claim 4

Apparatus in accordance with claim 2 wherein a first switch having first and second poles is closed when said first pulse duration type signal is in said first state, wherein said first switch is open when said first pulse duration type signal is in said second state and wherein said means for converting said first pulse duration type signal to said first clock signal and said means for supplying said first clock signal to the count input of said first counter comprises: a first oscillator having a first frequency; means for supplying the output of said first oscillator to said first pole of said first switch; and means for connecting said second pole of said first switch to the count input of said first counter, wherein said first clock signal has said first frequency and wherein said first clock signal is supplied to the count input of said first counter only when said first switch is closed.

Claim 5

Apparatus in accordance with claim 3 wherein a second switch having first and second poles is closed when said second pulse duration type signal is in said first state, wherein said second switch is open when said second pulse duration type signal is in said second state and wherein said means for converting said second pulse duration type signal to said second clock signal and said means for supplying said second clock signal to the count input of said second counter comprises: means for supplying the output of said first oscillator to said first pole of said second switch; and means for connecting said second pole of said second switch to the count input of said second counter, wherein said second clock signal has said first frequency and wherein said second clock signal is supplied to the count input of said second counter only when said second switch is closed.

Claim 6

Apparatus in accordance with claim 4 wherein said means for supplying said fixed period signal to the enabling input of said first counter and said means for supplying said fixed period signal to the enabling input of said second counter comprises: a second oscillator having a second frequency; a frequency divider; means for providing the output of said second oscillator to said frequency divider to thereby establish an output signal having said time period p; means for supplying the output from said frequency divider to the enabling input of said first counter as said fixed period signal; and means for supplying the output of said frequency divider to the enabling input of said second counter as said fixed period signal.

Claim 7

Apparatus in accordance with claim 5 additionally comprising: a delay circuit; means for providing the output from said second oscillator to said delay circuit as a clock signal; means for providing said fixed period signal to said delay circuit, wherein said delay circuit operates to delay the transition of said fixed period signal by a time determined by said second frequency; means for providing the fixed period signal, which has been delayed, from said delay circuit to the reset input of said first counter to thereby reset said first counter after said time period p; and means for providing the fixed period signal, which has been delayed, from said delay circuit to the reset input of said second counter to thereby reset said second counter after said time period p.

Claim 8

Apparatus in accordance with claim 6 wherein the count reached by said first counter is latched in said first counter at the end of said time period p by a transition of said fixed period signal, wherein said means for transferring the count reached by said first counter to said computer comprises means for reading the count latched in said first counter into said computer, wherein the count reached by said second counter is latched in said second counter at the end of said time period p by a transition of said fixed period signal and wherein said means for transferring the count reached by said second counter to said computer comprises means for reading the count latched in said second counter into said computer.

Claim 11

A method in accordance with claim 8 additionally comprising the steps of: generating a second pulse duration type signal, wherein said second pulse duration type signal is periodically repeated every said time period p, wherein said second pulse duration type signal is in said first state for a portion of said time period p and is in said second state for a portion of said time period p, wherein the length of time that said second pulse duration type signal is in said first state is representative of the value of a second variable, wherein said second pulse duration type signal is continuous and wherein said first pulse duration type signal and second pulse duration type signal are asynchronous; converting said second pulse duration type signal to a second clock signal when said second pulse duration signal is in said first state; supplying said second clock signal to a count input of a second counter; supplying said fixed period signal to an enable input of said second counter, wherein the count reached by said second counter during said time period p is representative of the time said second pulse duration type signal is in said first state; and transferring the count reached by said second counter to a computer to thereby transfer to said computer the value of said second variable.

Claim 12

A method in accordance with claim 9 wherein a first switch having first and second poles is closed when said first pulse duration type signal is in said first state, wherein said first switch is open when said first pulse duration type signal is in said second state and wherein said step of converting said first pulse duration type signal to said first clock signal and said step of supplying said first clock signal to the count input of said first counter comprises: supplying the output of a first oscillator having a first frequency to said first pole of said first switch; and connecting said second pole of said first switch to the count input of said first counter, wherein said first clock signal has said first frequency and wherein said first clock signal is supplied to the count input of said first counter only when said first switch is closed.

Claim 13

A method in accordance with claim 10 wherein a second switch having first and second poles is closed when said second pulse duration type signal is in said first state, wherein said second switch is open when said second pulse duration type signal is in said second state and wherein said step of converting said second pulse duration type signal to said second clock signal and said means for supplying said second clock signal to the count input of said second counter comprises: supplying the output of said first oscillator to said first pole of said second switch; and connecting said second pole of said second switch to the count input of said second counter, wherein said second clock signal has said first frequency and wherein said second clock signal is supplied to the count input of said second counter only when said second switch is closed.

Claim 14

A method in accordance with claim 11 wherein said step of supplying said fixed period signal to the enabling input of said first counter and said step of supplying said fixed period signal to the enabling input of said second counter comprises: providing the output of a second oscillator having a second frequency to a frequency divider to thereby establish an output signal having said time period p; supplying the output from said frequency divider to the enabling input of said first counter as said fixed period signal; and supplying the output of said frequency divider to the enabling input of said second counter as said fixed period signal.

Claim 15

A method in accordance with claim 12 additionally comprising the steps of: providing the output from said second oscillator to a delay circuit as a clock signal; providing said fixed period signal to said delay circuit, wherein said delay circuit operates to delay the transition of said fixed period signal by a time determined by said second frequency; providing the fixed period signal, which has been delayed, from said delay circuit to the reset input of said first counter to thereby reset said first counter after said time period p; and providing the fixed period signal, which has been delayed, from said delay circuit to the reset input of said second counter to thereby reset said second counter after said time period p.

Claim 16

A method in accordance with claim 13 wherein the count reached by said first counter is latched in said first counter at the end of said time period p by a transition of said fixed period signal, wherein said step of transferring the count reached by said first counter to said computer comprises reading the count latched in said first counter into said computer, wherein the count reached by said second counter is latched in said second counter at the end of said time period p by a transition of said fixed period signal and wherein said step of transferring the count reached by said second counter to said computer comprises reading the count latched in said second counter into said computer.