Clocked comparator

Claim 1

A clocked voltage comparator formed by means of transistors which each have a control electrode, a first main electrode and a second main electrode, said comparator comprising: a comparison stage for comparing an analog input voltage (V IN ) with an analog reference voltage (V REF ) and deriving an intermediate signal (V M ) and its complement (V M ), which stage comprises two transistors coupled as a differential pair, the input voltage and the reference voltage being applied to respective control electrodes of said transistors, whose first main electrodes are connected to a common terminal for applying a bias current and whose second main electrodes are each coupled to a first d.c. supply terminal via a load and supply the intermediate signal and its complement respectively; a latching stage coupled to the comparison stage for generating logic states in conformity with the output signals from the comparison stage, said latching stage comprising two transistors coupled together as a second differential pair forming a bistable latch, the signals received from branches of the comparison stage being applied to respective control electrodes of said latching-stage transistors, whose first main electrodes are connected to a common terminal and whose second main electrodes are cross-coupled to the control electrodes of the transistors of the second differential pair to form outputs of said latching stage, characterized in that: the terminal to which the first differential pair is connected is coupled to a second d.c. supply terminal via a current-source transistor, the terminal to which the second differential pair is connected is directly connected to the potential on the second d.c. supply terminal, the second differential pair is coupled to a third differential pair comprising two transistors coupled in parallel with the transistors of the second differential pair, and means for applying a clock signal to the control electrodes of the transistors of said third differential pair.