Circuit arrangement for telecommunications exchange systems, particularly telephone exchange systems, comprising information processing sequential logic systems and traffic measuring devices

Claim 1

In a circuit arrangement for telecommunications exchange systems, particularly telephone exchange systems, of the type which includes an information processing sequential logic system having a limited call handling capacity with respect to its information processing capacity, in which a buffer precedes the sequential logic system and serves for a temporary acceptance of information processing requests, in which a traffic measuring device is connected to the buffer for recognizing information processing traffic overloads of the sequential logic system and for averting such overloads by way of a request rejection device preceding the traffic measuring device, the request rejection device quantitatively dividing the incoming processing requests into acceptable processing requests which are supplied to the buffer and into unacceptable processing requests which are not supplied to the buffer, the improvement therein comprising: a first monitor connected to the buffer and operable to monitor the available buffer capacity; a first in-first out-last in-first out (FIFO-LIFO) memory connected to the request rejection device and to said first monitor and to the traffic measuring device and operable as a FIFO memory in response to being full and processing requests are stored in the buffer to mark processing requests it has rejected as non-acceptable, and operable as a LIFO memory in response to a predetermined number of processing requests residing in the buffer to output processing requests and mark the same as acceptable.