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US4647957A Expired / Lapsed US ⏱️ 0.0 years remaining

Latchup-preventing CMOS device

Assignee: Nokia Bell Labs
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Filing: 1986-04-21
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Granted: 1987-03-03
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Expires: 2006-04-21
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Abstract

Abstract A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 μm, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.

Inventors

  • 👤 Gerald A. Coquin
  • 👤 William T. Lynch
  • 👤 Louis C. Parrillo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 19:05
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 209 words
A device, comprising: a semiconductor substrate which includes first and second regions extending from a surface of said substrate, the conductivity type of the second region being opposite to that of the first region; said first region including a bulk region supporting a relatively thin layer having a doping level less than that of said bulk region, the interface between said bulk region and said relatively thin layer being substantially planar; and said relatively thin layer and said second region including, respectively, first and second field effect transistors, the channel conductivity type of said first transistor and of said second transistor being opposite, respectively, to the conductivity type of said first region and of said second region, characterized in that said device further comprises a trench containing a composition comprising polysilicon, formed in said substrate between said first and second transistors and extending from said surface through a portion, but less than all, of said layer, and said layer further includes a relatively heavily doped region, having a conductivity type the same as that of said layer, extending from a bottom of said trench to said bulk region, the largest lateral extent of said relatively heavily doped region being less than or equal to the thickness of said layer.
Claim 2
Independent Claim 209 words
A device, comprising: a semiconductor substrate which includes first and second regions extending from a surface of said substrate, the conductivity type of the second region being opposite to that of the first region; said first region including a bulk region supporting a relatively thin layer having a doping level less than that of said bulk region, the interface between said bulk region and said relatively thin layer being substantially planar; and said relatively thin layer and said second region including, respectively, first and second field effect transistors, the channel conductivity type of said first transistor and of said second transistor being opposite, respectively, to the conductivity type of said first region and of said second region, characterized in that said device further comprises a trench containing a composition comprising polysilicon, formed in said substrate between said first and second transistors and extending from said surface through a portion, but less than all, of said layer, and said layer further includes a relatively heavily doped region, having a conductivity type the same as that of said layer, extending from a bottom of said trench to said bulk region, the largest lateral extent of said relatively heavily doped region being less than or equal to the thickness of said layer.
Claim 3
Dependent Claim 47 words
The device of claim 1 wherein said trench includes a sidewall which, in cross-section, is substantially linear and forms an angle with a perpendicular drawn to said surface at the intersection of said sidewall and said surface which ranges from about 5 degrees to about 10 degrees.
Claim 4
Dependent Claim 12 words
The device of claim 1 wherein said semiconductor substrate is of silicon.
Claim 5
Dependent Claim 17 words
The device of claim 1 wherein a width of said trench is less than about 10 μm.
Claim 6
Dependent Claim 17 words
The device of claim 1 wherein a width of said trench is less than about 4 μm.
Claim 7
Dependent Claim 55 words
The device of claim 1 wherein a doping level of said bulk region and of said relatively heavily doped region ranges from about 10 17 cm -3 to about 10 21 cm -3 , while a doping level of said layer ranges from about 10 14 cm -3 to about 10 17 cm -3 .
Claim 8
Dependent Claim 20 words
The device of claim 1 wherein a thickness of said layer ranges from about 1 μm to about 10 μm.
Claim 9
Dependent Claim 20 words
The device of claim 1 wherein a depth of said relatively heavily doped region is less than about 4 μm.
Claim 10
Dependent Claim 15 words
The device of claim 1 wherein said layer is epitaxially grown on said bulk region.
Claim 11
Dependent Claim 28 words
The device of claim 1 wherein an integrated doping level of said second region ranges from about 10 12 cm -2 to about 10 15 cm -2 .
Claim 12
Dependent Claim 19 words
The device of claim 1 further comprising a layer of dielectric material covering an interior surface of said trench.

References Cited (Backward Citations)

US4231057A Cited
US4477310A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-03-02 1990-09-01 1991-03-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-03-02 1994-09-01 1995-03-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-03-02 1998-09-01 1999-03-03 $7700.00 Window Closed / Lapsed

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