Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
457 words
In a synchronization apparatus in a telecommunication system of the time division multiplex type, in which information is transmitted in assigned time slots in one-way data transmission between a plurality of equal transmitter/receiver modules (A-N) connected to a common bus, for enabling transmission through the bus from arbitrary transmitters (S) to arbitrary receivers (R) in adjacent time slots without time difference between transmission sequences in respective time slots, the improvement in which: said bus is divided into first, final and intermediate sections; said transmitters (S) being connected in a given order to said first section (B1), each module having a transmitter output and bus input with a predetermined distance therebetween so that a fixed time delay is obtained which is the same for each module, there being a total fixed time delay through said first bus section (B1) dependent on the number of modules (A-N) connected thereto; said receivers (R) being connected to said final bus section (B3) in the same order as the transmitters, each module having a bus output and receiver output with a predetermined distance therebetween so that a fixed time delay is obtained which is the same for each module, the total fixed time delay through said final section (B3) being dependent on the number of modules (A-N) connected thereto; said intermediate section (B2) having variable length and extending from the last connected transmitter (S) to the first connected receiver (R), the length of said intermediate section, in relation to the size of said fixed time delays, being adjusted to give a selectable, predetermined total time delay between transmitter and receiver in the same module; each of said modules (A-N) including a clock signal unit (CL) common to the associated transmitter and receiver, said clock signal unit sending, apart from internal clock signals (CS) each time the module is selected as master, a frame synchronization pulse (FS) once per frame to an input of said bus via a bus transmitter (BS), said frame synchronizing pulse (FS) for synchronizing remaining slave modules being sent in parallel with the data in parallel with the data information from the associated transmitter, and a time slot memory (TM) storing data which is written in and read out from and to the bus under control of signals from a control memory (CM) connected to the address inputs of the time slot memory (TM) as well as clock signals, data information being read out to the bus via a first latch circuit (L1) and the bus transmitter (BS), and data being written in to the time slot memory (TM) from the bus via a bus receiver (BR) and a second latch circuit (L2), said read-out and write-in respectively being controlled by signals from the common clock signal unit (CL).
Claim 2
Dependent Claim
457 words
In a synchronization apparatus in a telecommunication system of the time division multiplex type, in which information is transmitted in assigned time slots in one-way data transmission between a plurality of equal transmitter/receiver modules (A-N) connected to a common bus, for enabling transmission through the bus from arbitrary transmitters (S) to arbitrary receivers (R) in adjacent time slots without time difference between transmission sequences in respective time slots, the improvement in which: said bus is divided into first, final and intermediate sections; said transmitters (S) being connected in a given order to said first section (B1), each module having a transmitter output and bus input with a predetermined distance therebetween so that a fixed time delay is obtained which is the same for each module, there being a total fixed time delay through said first bus section (B1) dependent on the number of modules (A-N) connected thereto; said receivers (R) being connected to said final bus section (B3) in the same order as the transmitters, each module having a bus output and receiver output with a predetermined distance therebetween so that a fixed time delay is obtained which is the same for each module, the total fixed time delay through said final section (B3) being dependent on the number of modules (A-N) connected thereto; said intermediate section (B2) having variable length and extending from the last connected transmitter (S) to the first connected receiver (R), the length of said intermediate section, in relation to the size of said fixed time delays, being adjusted to give a selectable, predetermined total time delay between transmitter and receiver in the same module; each of said modules (A-N) including a clock signal unit (CL) common to the associated transmitter and receiver, said clock signal unit sending, apart from internal clock signals (CS) each time the module is selected as master, a frame synchronization pulse (FS) once per frame to an input of said bus via a bus transmitter (BS), said frame synchronizing pulse (FS) for synchronizing remaining slave modules being sent in parallel with the data in parallel with the data information from the associated transmitter, and a time slot memory (TM) storing data which is written in and read out from and to the bus under control of signals from a control memory (CM) connected to the address inputs of the time slot memory (TM) as well as clock signals, data information being read out to the bus via a first latch circuit (L1) and the bus transmitter (BS), and data being written in to the time slot memory (TM) from the bus via a bus receiver (BR) and a second latch circuit (L2), said read-out and write-in respectively being controlled by signals from the common clock signal unit (CL).
Claim 3
Dependent Claim
45 words
Apparatus as claimed in claim 1, wherein said control signals from the clock signal unit (CL) for reading-out and writing-in of information to and from the bus consists of clock signals from the same basic clock signal in a given phase relationship to each other.
Claim 4
Dependent Claim
27 words
Apparatus as claimed in claim 1, wherein said first bus section (B1) and said final bus section (B3) are arranged on parallel conductors in the same cable.
Claim 5
Dependent Claim
49 words
Apparatus as claimed in claim 1, including and wherein a phase comparator (PC) receives the frame synchronization signal from the bus and compares it with the locally generated frame synchronization pulse, the difference being given as a voltage (U) which corrects the phase position of the clock signal unit.