US4646123A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Latchup-preventing CMOS device
Assignee: Nokia Bell Labs
•
Filing: 1986-04-21
•
Granted: 1987-02-24
•
Expires: 2006-04-21
Abstract
Abstract A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 μm, as well as a method for fabricating the device, is disclosed. The inventive CMOS device includes a latchup-preventing, polysilicon-filled trench formed in the semiconductor substrate between the n- and p-channel FETs of the device. The polysilicon-filled trench is essentially free of crack-inducing voids, and achieves a width less than 10 μm, because the angle between the trench sidewall and a perpendicular drawn to the substrate surface is greater than, or equal to, about 5 degrees but less than about 10 degrees. Also, a thickness of the polysilicon deposited into the trench is greater than half the width of the trench.
Inventors
- 👤 William T. Lynch
- 👤 Louis C. Parrillo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 00:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
145 words
A device, comprising: a semiconductor substrate which includes first and second regions extending from a surface of said substrate, the conductivity type of the second region being opposite to that of the first region; and said first and second regions including, respectively, first and second field effect transistors, the channel conductivity type of said first transistor and of said second transistor being opposite, respectively, to the conductivity type of said first region and of said second region, characterized in that said device further comprises a trench containing a composition comprising polysilicon, extending from said surface into said substrate between said first and second transistors, said trench including a sidewall which, in cross-section, is substantially linear and forms an angle with a perpendicular drawn to said surface at the intersection of said sidewall and said surface which ranges from about 5 degrees to about 10 degrees.
Claim 2
Independent Claim
145 words
A device, comprising: a semiconductor substrate which includes first and second regions extending from a surface of said substrate, the conductivity type of the second region being opposite to that of the first region; and said first and second regions including, respectively, first and second field effect transistors, the channel conductivity type of said first transistor and of said second transistor being opposite, respectively, to the conductivity type of said first region and of said second region, characterized in that said device further comprises a trench containing a composition comprising polysilicon, extending from said surface into said substrate between said first and second transistors, said trench including a sidewall which, in cross-section, is substantially linear and forms an angle with a perpendicular drawn to said surface at the intersection of said sidewall and said surface which ranges from about 5 degrees to about 10 degrees.
Claim 3
Dependent Claim
12 words
The device of claim 1 wherein said semiconductor substrate is of silicon.
Claim 4
Dependent Claim
17 words
The device of claim 1 wherein a width of said trench is less than about 10 μm.
Claim 5
Dependent Claim
17 words
The device of claim 1 wherein a width of said trench is less than about 4 μm.
Claim 6
Dependent Claim
20 words
The device of claim 1 wherein a depth of said trench ranges from about 2 μm to about 30 μm.
Claim 7
Dependent Claim
27 words
The device of claim 1 wherein a doping level of said first region ranges from about 10 15 cm -3 to about 10 17 cm -3 .
Claim 8
Dependent Claim
28 words
The device of claim 1 wherein an integrated doping level of said second region ranges from about 10 12 cm -2 to about 10 15 cm -2 .
Claim 9
Dependent Claim
19 words
The device of claim 1 further comprising a layer of dielectric material covering an interior surface of said trench.
Claim 10
Dependent Claim
89 words
The device of claim 1, wherein: said first region includes a bulk region supporting a relatively thin layer containing said second region, the interface between said bulk region and said relatively thin layer being substantially planar, and the conductivity type of said thin layer, external to said second region, being the same as that of the bulk region, the doping level of said thin layer being less than that of said bulk region; and said trench extends through the thickness of said layer at least to said bulk region.
Claim 11
Dependent Claim
47 words
The device of claim 9 wherein a doping level of said layer ranges from about 10 14 cm -3 to about 10 17 cm -3 and a doping level of said bulk region ranges from about 10 17 cm -3 to about 10 21 cm -3 .
Claim 12
Dependent Claim
20 words
The device of claim 9 wherein a thickness of said layer ranges from about 1 μm to about 10 μm.
Claim 13
Dependent Claim
15 words
The device of claim 9 wherein said layer is epitaxially grown on said bulk region.
References Cited (Backward Citations)
US4231057A
Cited
US4477310A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-23 | 1990-08-25 | 1991-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-23 | 1994-08-25 | 1995-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-23 | 1998-08-25 | 1999-02-24 | $7700.00 | Window Closed / Lapsed |