Apparatus for correcting errors

Claim 1

An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having different kinds of information and l parity symbols is transmitted as a unit, said processing consisting of an encoding process with respect to a first error detection code or an error correction code for generating a redundancy code of k symbols regarding said n symbols, and an encoding process with respect to a second error correction code for generating a redundancy code of one symbol regarding (n+k+m) symbols, wherein said error correcting apparatus comprising: a first decoder with respect to said first error detection code or said error correction code to which said redundancy code of (n+k) symbols is supplied and which generates a first flag signal indicative of the error state by at least performing the error detection wherein said first flag signal is the signal indicating the number (including 0) of error symbols with respect to the (n+k) symbols; and a second decorder with respect to said second error correction code to which (n+k) symbols corrected by said first decoder and (m+l) symbols received are supplied and which generates a second flag signal representing the error state by performing the error detection, wherein said second flag signal is the signal representing the number (including 0) of error symbols before the error correction by said second decoder with respect to the (n+k+m+l) symbols, and performs the error correction by comparing said first and second flag signals and the error correction processing by said second decoder is controlled in accordance with the result of said comparison.

Claim 2

An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having different kinds of information and l parity symbols is transmitted as a unit, said processing consisting of an encoding process with respect to a first error detection code or an error correction code for generating a redundancy code of k symbols regarding said n symbols, and an encoding process with respect to a second error correction code for generating a redundancy code of one symbol regarding (n+k+m) symbols, wherein said error correcting apparatus comprising: a first decoder with respect to said first error detection code or said error correction code to which said redundancy code of (n+k) symbols is supplied and which generates a first flag signal indicative of the error state by at least performing the error detection wherein said first flag signal is the signal indicating the number (including 0) of error symbols with respect to the (n+k) symbols; and a second decorder with respect to said second error correction code to which (n+k) symbols corrected by said first decoder and (m+l) symbols received are supplied and which generates a second flag signal representing the error state by performing the error detection, wherein said second flag signal is the signal representing the number (including 0) of error symbols before the error correction by said second decoder with respect to the (n+k+m+l) symbols, and performs the error correction by comparing said first and second flag signals and the error correction processing by said second decoder is controlled in accordance with the result of said comparison.

Claim 4

An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having difference kinds of information and l parity symbols is transmitted as a unit, said processing consisting of an encoding process with respect to a first error correction code for generating a redundancy code of k symbols regarding said n symbols, and an encoding process with respect to a second error correction code for generating a redundancy code of one symbol regarding (n+k+m) symbols, wherein said error correcting apparatus comprising: a first decoder with respect to said second error correction code to which said (n+k+m+l) symbols are supplied and which generates a first flag signal indicative of the number (including 0) of error symbols and the error locations by performing the error detection regarding the (n+k+m+l) symbols and performs the error correction regarding the (m+l) symbols; a second decoder with respect to said first error correction code to which (n+k) symbols transmitted through said first decoder are supplied and which generates a second flag signal representing the number (including 0) of error symbols and performs the error correction suing said first and second flag signals; and a third decoder with respect to said second error correction code to which the (n+k+m+l) symbols are supplied from said first and second decoders and which performs the error correction using said second flag signal.

Claim 5

An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having difference kinds of information and l parity symbols is transmitted as a unit, said processing consisting of an encoding process with respect to a first error correction code for generating a redundancy code of k symbols regarding said n symbols, and an encoding process with respect to a second error correction code for generating a redundancy code of one symbol regarding (n+k+m) symbols, wherein said error correcting apparatus comprising: a first decoder with respect to said second error correction code to which said (n+k+m+l) symbols are supplied and which generates a first flag signal indicative of the number (including 0) of error symbols and the error locations by performing the error detection regarding the (n+k+m+l) symbols and performs the error correction regarding the (m+l) symbols; a second decoder with respect to said first error correction code to which (n+k) symbols transmitted through said first decoder are supplied and which generates a second flag signal representing the number (including 0) of error symbols and performs the error correction suing said first and second flag signals; and a third decoder with respect to said second error correction code to which the (n+k+m+l) symbols are supplied from said first and second decoders and which performs the error correction using said second flag signal.

Claim 7

An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having different kinds of information and l parity symbols is transmitted as a unit, said processing consisting of: an encoding process with respect to a first error detection code or an error correction code for generating a redundancy code of k symbols regarding said n symbols, and an encoding process with respect to a second error correction code for generating a redundancy code of one symbol regarding (n+k+m) symbols, wherein said error correcting apparatus comprises: a first decoder with respect to said first error detection code or said error correction code to which said redundancy code of (n+k) symbols is supplied and which generates a first flag signal indicative of the error state by at least performing the error detection wherein said first flag signal is the signal indicating the number (including 0) of error symbols with respect to the (n+k) symbols; and a second decoder with respect to said second error correction code to which (n+k) symbols corrected by said first decoder and (m+l) symbols received are supplied and which generates a second flag signal representing the error state by performing the error detection, wherein said second flag signal is the signal representing the error locations among the (n+k+m+l) symbols before the error correction by said second decoder, and performs the error correction by comparing said first and second flag signals and the error correction processing by said second decoder is controlled in accordance with the result of said comparison.

Claim 8

An apparatus for correcting errors in data which has, as a unit, (n+k+m+l) symbols subjected to processing for error correction coding when data consisting of n symbols and m symbols having different kinds of information and l parity symbols is transmitted as a unit, said processing consisting of: an encoding process with respect to a first error detection code or an error correction code for generating a redundancy code of k symbols regarding said n symbols, and an encoding process with respect to a second error correction code for generating a redundancy code of one symbol regarding (n+k+m) symbols, wherein said error correcting apparatus comprises: a first decoder with respect to said first error detection code or said error correction code to which said redundancy code of (n+k) symbols is supplied and which generates a first flag signal indicative of the error state by at least performing the error detection wherein said first flag signal is the signal indicating the number (including 0) of error symbols with respect to the (n+k) symbols; and a second decoder with respect to said second error correction code to which (n+k) symbols corrected by said first decoder and (m+l) symbols received are supplied and which generates a second flag signal representing the error state by performing the error detection, wherein said second flag signal is the signal representing the error locations among the (n+k+m+l) symbols before the error correction by said second decoder, and performs the error correction by comparing said first and second flag signals and the error correction processing by said second decoder is controlled in accordance with the result of said comparison.