US4644186A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fast switching circuit for lateral PNP transistors
Assignee: National Semiconductor Corp
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Filing: 1984-08-20
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Granted: 1987-02-17
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Expires: 2004-08-20
Abstract
Abstract A circuit (100) is shown which provides a large turn-on current drive to the base of a lateral PNP transistor (218) by forcing a large voltage drop across the base-emitter junction of the lateral PNP transistor in order to quickly turn on the PNP transistor. A current sensing circuit (203, 166) determines when the collector current in the PNP transistor is sufficient for proper operation of the rest of the circuitry dependent upon this PNP transistor. The current sensing circuitry then limits the base drive applied to the PNP transistor to the current level necessary to maintain the required quiescent collector current in the PNP transistor. In addition, means (190, 200) are provided to quickly clamp the base of the PNP transistor to the emitter of the PNP transistor thereby quickly turning off the PNP transistor.
Inventors
- 👤 Sivakumar Sivasothy
- 👤 Ramanatha V. Balakrishnan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:35
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/0412; H03K17/04126
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
587 words
An output buffer having a data input terminal, an enable input terminal and an output terminal, comprising: a first bipolar transistor of a first doping configuration having a collector, an emitter connected to a first potential and a base; a high current source having a high current output lead connected to said base of said first bipolar transistor and having a first control input lead, said high current source providing a high current in response to signals provided on said first control input lead; a low current source having a low current output lead connected to said base of said first bipolar transistor, and having a second control input lead, said low current source providing current in response to signals provided on said second control input lead; current sensing means for sensing the collector current in said first bipolar transistor, said current sensing means having a first control output lead connected to said first control input lead, a second control output lead connected to said second control input lead, and a master control input lead connected to said enable input terminal, said current sensing means providing a first set of output signals on said first and second control output leads in response to a first input signal provided on said master control input terminal and a first selected current in said first bipolar transistor thereby causing said high current source and said current source to provide current, thereby causing said first bipolar transistor to turn on quickly, said current sensing means providing a second set of output signals on said first and second control output leads in response to said first input signal on said master control input lead and a second selected current in said first bipolar transistor thereby causing said high current source to not provide current and said low current source to provide current thereby causing said first bipolar transistor to remain on, and said current sensing means providing a third set of output signals on said first and second control output leads in respnse to a second input signal on said master control input lead thereby causing said high current source and said low current source to not provide current and causing said first bipolar transistor to turn off; a second bipolar transistor of a second doping configuration opposite to said first doping configuration having a collector connected to said first potential, a base connected to said collector of said first bipolar transistor and an emitter connected to said output terminal; a third bipolar transistor of said second doping configuration having a collector connected to said collector of said first bipolar transistor, a base connected to said data input terminal, and having an emitter; a fourth bipolar transistor of said second doping configuration having a collector connected to said output terminal, a base connected to said emitter of said third bipolar transistor, and an emitter connected to a reference potential; first switching means having a first current handling terminal connected to said base of said first bipolar transistor, a second current handling terminal connected to said emitter of said first bipolar transistor, and having a control terminal; and first bias pulse means having an input lead connected to said enable input terminal, and a pulse output lead connected to said control terminal of said first switch means for providing a bias pulse to said control terminal of said first switch means in respnse to said second input signal of said enable input terminal thereby causing said first bipolar transistor to turn off quickly.
Claim 2
Dependent Claim
587 words
An output buffer having a data input terminal, an enable input terminal and an output terminal, comprising: a first bipolar transistor of a first doping configuration having a collector, an emitter connected to a first potential and a base; a high current source having a high current output lead connected to said base of said first bipolar transistor and having a first control input lead, said high current source providing a high current in response to signals provided on said first control input lead; a low current source having a low current output lead connected to said base of said first bipolar transistor, and having a second control input lead, said low current source providing current in response to signals provided on said second control input lead; current sensing means for sensing the collector current in said first bipolar transistor, said current sensing means having a first control output lead connected to said first control input lead, a second control output lead connected to said second control input lead, and a master control input lead connected to said enable input terminal, said current sensing means providing a first set of output signals on said first and second control output leads in response to a first input signal provided on said master control input terminal and a first selected current in said first bipolar transistor thereby causing said high current source and said current source to provide current, thereby causing said first bipolar transistor to turn on quickly, said current sensing means providing a second set of output signals on said first and second control output leads in response to said first input signal on said master control input lead and a second selected current in said first bipolar transistor thereby causing said high current source to not provide current and said low current source to provide current thereby causing said first bipolar transistor to remain on, and said current sensing means providing a third set of output signals on said first and second control output leads in respnse to a second input signal on said master control input lead thereby causing said high current source and said low current source to not provide current and causing said first bipolar transistor to turn off; a second bipolar transistor of a second doping configuration opposite to said first doping configuration having a collector connected to said first potential, a base connected to said collector of said first bipolar transistor and an emitter connected to said output terminal; a third bipolar transistor of said second doping configuration having a collector connected to said collector of said first bipolar transistor, a base connected to said data input terminal, and having an emitter; a fourth bipolar transistor of said second doping configuration having a collector connected to said output terminal, a base connected to said emitter of said third bipolar transistor, and an emitter connected to a reference potential; first switching means having a first current handling terminal connected to said base of said first bipolar transistor, a second current handling terminal connected to said emitter of said first bipolar transistor, and having a control terminal; and first bias pulse means having an input lead connected to said enable input terminal, and a pulse output lead connected to said control terminal of said first switch means for providing a bias pulse to said control terminal of said first switch means in respnse to said second input signal of said enable input terminal thereby causing said first bipolar transistor to turn off quickly.
Claim 3
Dependent Claim
15 words
An output buffer as in claim 1 wherein said first switch means comprises a transistor.
Claim 4
Dependent Claim
17 words
An output buffer as in claim 1 wherein said first bipolar transistor is a lateral PNP transistor.
Claim 5
Dependent Claim
17 words
An output buffer as in claim 1 wherein said first bipolar transistor is a lateral PNP transistor.
Claim 6
Dependent Claim
107 words
An output buffer as in claim 1 further comprising: second switch means having a first current handling terminal connected to said reference potential, a second current handling terminal connected to said collector of said first bipolar transistor, and having a control terminal; and second bias pulse means having an input lead connected to said enable input terminal, and a pulse output lead connected to said control terminal of said second switch means for providing a bias pulse to said control terminal of said second switch means in response to said second input signal on said enable input terminal, thereby causing said fourth transistor to turn off quickly.
Claim 7
Dependent Claim
14 words
An output buffer as in claim 5 wherein said switch means comprises a transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |