US4643527A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for the production of a substrate for an electrically controlled device and display screen produced from such a substrate
Assignee: TOMSON-CSF 173
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Filing: 1984-08-20
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Granted: 1987-02-17
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Expires: 2004-08-20
Abstract
Abstract The invention relates to a process for the production of a substrate for an electrically controlled device such as a display screen, said substrate integrating non-linear elements and control elements of the elementary display points. The invention relates to the production of a substrate, in its active part, has non-linear elements associated with each image element and produced from amorphous silicon and, in its peripheral part, polycrystalline silicon controlled elements. Initially the substrate has amorphous silicon layers, the peripheral crystallization being obtained by annealing in a temperature gradient furnace.
Inventors
- 👤 Jose Magarino
- 👤 Nicolas Szydlo
- 👤 Michel Hareng
- 👤 Pierre Landouar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:16
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0221; H10D86/0223; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1365; H10D86/40; H10D86/60; H10P; H10P95/00; H10P95/90; Y; Y10; Y10S; Y10S359/00; Y10S359/90
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
97 words
A process for producing a silicon substrate useful for the incorporation therein of transistors and diodes comprising the steps of positioning an amorphous silicon substrate in a furnace which has a non-uniform temperature distribution such that edge regions of the substrate are in a zone at a temperature high enough to convert the amorphous silicon to the polycrystalline form while the interior regions of the substrate are in a zone at a temperature insufficiently high to crystallize the amorphous silicon, and removing the substrate from the furnace after desired edge regions of the substrate have been crystallized.
Claim 2
Dependent Claim
97 words
A process for producing a silicon substrate useful for the incorporation therein of transistors and diodes comprising the steps of positioning an amorphous silicon substrate in a furnace which has a non-uniform temperature distribution such that edge regions of the substrate are in a zone at a temperature high enough to convert the amorphous silicon to the polycrystalline form while the interior regions of the substrate are in a zone at a temperature insufficiently high to crystallize the amorphous silicon, and removing the substrate from the furnace after desired edge regions of the substrate have been crystallized.
Claim 3
Dependent Claim
29 words
The process of claim 1 followed by the forming of thin-film transistors in the polycrystalline edge regions of the substrate and of nonlinear diodes in the amorphous interior region.
Claim 4
Dependent Claim
41 words
The process of claim 1 in which the amorphous silicon substrate comprises in succession a relatively lightly doped first layer, a relatively heavily draped second layer, and a relatively lightly doped third layer, each formed by the thermal decomposition of silane.
Claim 5
Dependent Claim
32 words
The process of claim 3 in which the amorphouse silicon substrate had earlier been exposed to a hydrogen plasma for post-hydrogenation of the amorphous silicon formed by the thermal decomposition of silane.
Claim 6
Dependent Claim
82 words
A process for making a matrix access display screen having image elements at intersections of row and column access electrodes including forming a substrate in accordance with claim 1, forming in the amorphous regions a plurality of oppositedly poled diode pairs and in the polycrystalline regions a plurality of thin filrm transistors, incorporating the transistors into circuitry with the row and column electrodes of the display screen and incorporating the diode pairs in series with electrooptical image elements of the display screen.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |