US4641358A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Optical mark reader
Assignee: United States Department of the Air Force
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Filing: 1984-10-18
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Granted: 1987-02-03
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Expires: 2004-10-18
Abstract
Abstract The reading of the presence or absence of a pencil or similar mark at various locations on a sheet of paper is accomplished by an optical Mark-Reader comprised of a completely solid state sensing mechanism with no moving parts. The Optical Mark Reader (OMR) contains a matrix of light sensitive transistors with their geometry and logic circuits capable of being tailored for a plurality of answer sheets. The internal logic circuits enable certain sections of the page to be read, generate a delay time while the data is being gathered, tell the host computer when the data is complete, and resets the OMR operator control system for successive page readings. Finally, the internal logic circuits and output bus of the OMR takes the "raw" data from the answer sheets and presents information on an output bus in a format allowing any computer (even a micro-computer) to be the host computer.
Inventors
- 👤 Bruce R. Archambeault
- 👤 David P. Rancour
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:18
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/10; G06K7/10544; G06K7/10821; G06K7/1093; G06K17/00; G06K17/0032
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
189 words
An apparatus for use with a host computer for detecting and locating discrete opaque regions a distal surface of a translucent sheet member, said apparatus comprising: an illumination source illuminating said surface with electromagnetic wave energy; a sensing means, said sensing means containing sets of an odd number of light sensitive transistor circuits, each of said sets being fixed in a proximate relationship to the distal surface of said sheet member, each set thereof being in register with a discrete region of said sheet member and having an output responsive to translucent and opaque conditions thereof; voting circuits, each of which are electrically connected to one of said sets of said light sensitive transistor circuits in said sensing means, each of said voting circuits generating a vote signal of logic 1 when a majority of said light sensitive transistors in the set are covered by a mark and a logic 0 when a majority of said light sensitive transistor are not covered by a mark; and a word output logic circuit which receives said vote signals from said voting circuits and reports said vote signals to said host computer.
Claim 2
Independent Claim
189 words
An apparatus for use with a host computer for detecting and locating discrete opaque regions a distal surface of a translucent sheet member, said apparatus comprising: an illumination source illuminating said surface with electromagnetic wave energy; a sensing means, said sensing means containing sets of an odd number of light sensitive transistor circuits, each of said sets being fixed in a proximate relationship to the distal surface of said sheet member, each set thereof being in register with a discrete region of said sheet member and having an output responsive to translucent and opaque conditions thereof; voting circuits, each of which are electrically connected to one of said sets of said light sensitive transistor circuits in said sensing means, each of said voting circuits generating a vote signal of logic 1 when a majority of said light sensitive transistors in the set are covered by a mark and a logic 0 when a majority of said light sensitive transistor are not covered by a mark; and a word output logic circuit which receives said vote signals from said voting circuits and reports said vote signals to said host computer.
Claim 3
Dependent Claim
175 words
An apparatus for detecting and locating discrete opaque regions on one surface of a translucent sheet member as defined in claim 1 wherein said voting circuits comprise: a plurality of open collector NAND gates, each electrically connected with one of said sets of an odd number of light sensitive transistor circuits and receiving the output signal from a selected row light sensitive transistor circuits in said sensing means, said light sensitive transistor circuits being in location corresponding to a position where a mark will be made on selected columns in a particular row on said sheet of paper, said open collector NAND gates each providing a logic 1 when a mark covers said selected light sensitive transistor circuit, and a logic 0 when no mark covers said selected light sensitive transistor circuit, said plurality of open collector NAND gates thereby acting as a counter to report an absence of a mark when all of said light sensitive transistor circuits indicate its absence and reporting the presence of a mark on said translucent sheet member otherwise.
Claim 4
Dependent Claim
92 words
An apparatus for detecting and locating discrete opaque regions on one surface of a translucent sheet member as defined in claim 2 wherein each of said sets of odd number of light sensitive transistor circuits comprises: three light sensitive transistors which are fixed in proximity with each other and provide an electrical output signal in response to said illumination source when not covered by a mark on said translucent sheet member, said three light sensitive transistors not producing an electrical output signal when covered by a mark on said translucent sheet member.
Claim 5
Dependent Claim
96 words
An apparatus for detecting and locating discrete opaque regions on one surface of a translucent sheet member as defined in claim 1 wherein said voting circuit comprises a plurality of binary counters, each electrically connected with one of said sets of an odd number of light sensitive transistor circuits to receive and count output signals produced by them, each of said binary counters reporting a logic 1 when a majority of said sets of light sensitive transistors are covered by a mark and said binary counters producing no output signal and reporting a logic 0 otherwise.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-02 | 1990-08-04 | 1991-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-02 | 1994-08-04 | 1995-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-02 | 1998-08-04 | 1999-02-03 | $7700.00 | Window Closed / Lapsed |