US4640888A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Alignment mark on a semiconductor and a method of forming the same
Assignee: Oki Electric Industry Co Ltd
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Filing: 1985-01-17
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Granted: 1987-02-03
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Expires: 2005-01-17
Abstract
Abstract An alignment mark formed on a semiconductor wafer is disclosed. The mark comprises a mark member provided on a base region and a reflection changing portion provided on the mark member. The reflection changing portion has slightly inclined side walls.
Inventors
- 👤 Yoshio Itoh
- 👤 Hiroshi Ohtsuka
- 👤 Tadashi Nishimuro
- 👤 Norio Moriyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:08
CPC Classifications
G; G03; G03F; G03F9/00; G03F9/70; G03F9/7073; G03F9/7076; H; H10; H10W; H10W46/00; H10W46/501
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
152 words
A method of forming an alignment mark for registering a semiconductor wafer, said wafer being registered by scanning an incident light across the alignment mark, the method comprising the steps of: preparing a semiconductor substrate; providing on the surface of the semiconductor substrate a grid line region to serve as a section for dividing the semiconductor wafer into a plurality of chips; providing a first island region of polycrystalline silicon on the grid line region; providing a film of phospho-silicate glass on the surfaces of the first island region and the semiconductor substrate; subjecting the phospho-silicate glass film to photolithographic etching for forming a second island region adjacent to the first island region, thereby forming an elongated slit having a width of 1 μm or less between the first and second island regions, said elongated slit serving as the alignment mark by reflecting as only one peak the incident light scanning thereacross.
Claim 2
Independent Claim
152 words
A method of forming an alignment mark for registering a semiconductor wafer, said wafer being registered by scanning an incident light across the alignment mark, the method comprising the steps of: preparing a semiconductor substrate; providing on the surface of the semiconductor substrate a grid line region to serve as a section for dividing the semiconductor wafer into a plurality of chips; providing a first island region of polycrystalline silicon on the grid line region; providing a film of phospho-silicate glass on the surfaces of the first island region and the semiconductor substrate; subjecting the phospho-silicate glass film to photolithographic etching for forming a second island region adjacent to the first island region, thereby forming an elongated slit having a width of 1 μm or less between the first and second island regions, said elongated slit serving as the alignment mark by reflecting as only one peak the incident light scanning thereacross.
Claim 3
Dependent Claim
28 words
A method as claimed in claim 1, wherein the first and second island regions have a width of about 1 μm and a height of about 0.3 μm.
References Cited (Backward Citations)
US3690881A
Cited
US4343878A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-02 | 1990-08-04 | 1991-02-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-02 | 1994-08-04 | 1995-02-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-02 | 1998-08-04 | 1999-02-03 | $7700.00 | Window Closed / Lapsed |