US4637036A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for a data acquisition circuit of a PCM processor and a method for improving waveform of PCM signal eye pattern
Assignee: Victor Company of Japan Ltd
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Filing: 1984-05-18
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Granted: 1987-01-13
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Expires: 2004-05-18
Abstract
Abstract A circuit arrangement comprises a frequency response control circuit for controlling the level around a particular frequency of an input PCM signal in accordance with a control signal which is produced as a function of the difference between levels of positive peaks and/or negative peak corresponding to a logic bit pattern 1010 of a data synchronous signal of the PCM signal having a predetermined format. The level detection may be performed by a plurality of sample-and-hold circuits, and the difference is obtained by way of an adder-subtractor. The circuit may be arranged to constitute either a feedback loop in which level detection is effected by using a frequency response controlled PCM signal, or a feedforward system in which level detection is effected by using the input PCM signal whose frequency response has not been controlled. An output signal from the frequency response control circuit is then applied to two comparators of a conventional data acquisition circuit.
Inventors
- 👤 Harukuni Kobari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:38
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10527; H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
227 words
A circuit arrangement for a data acquisition circuit of a PCM processor responsive to a PCM signal of a predetermined format and having a 1010 synchronizing signal and a digital signal both arranged in series of data blocks so that each 1010 synchronizing signal is followed by a corresponding data block, said circuit arrangement comprising: (a) first means responsive to bits of said 1010 synchronizing signal of signal PCM signal for producing timing signals; (b) second means responsive to said timing signals for detecting positive and/or negative peak levels of bits of only said 1010 synchronizing signal of said PCM signal; (c) third means responsive to said second means for producing a control signal representative of detected peak levels of said 1010 synchronizing signal; and (d) a frequency response control means responsive to said control signal for changing the frequency response to said PCM signal such that the frequency response to said PCM signal is controlled by said control signal which is produced using the peak levels of said 1010 synchronizing signal which immediately precedes each of said data blocks, said third means comprising at least two sample-and hold circuits used for respectively sampling and holding the levels of two successive positive-going peaks corresponding to "1" in said 1010 synchronizing signal so that said control signal represents a difference between amplitudes of said two successive positive-going peaks.
Claim 2
Dependent Claim
227 words
A circuit arrangement for a data acquisition circuit of a PCM processor responsive to a PCM signal of a predetermined format and having a 1010 synchronizing signal and a digital signal both arranged in series of data blocks so that each 1010 synchronizing signal is followed by a corresponding data block, said circuit arrangement comprising: (a) first means responsive to bits of said 1010 synchronizing signal of signal PCM signal for producing timing signals; (b) second means responsive to said timing signals for detecting positive and/or negative peak levels of bits of only said 1010 synchronizing signal of said PCM signal; (c) third means responsive to said second means for producing a control signal representative of detected peak levels of said 1010 synchronizing signal; and (d) a frequency response control means responsive to said control signal for changing the frequency response to said PCM signal such that the frequency response to said PCM signal is controlled by said control signal which is produced using the peak levels of said 1010 synchronizing signal which immediately precedes each of said data blocks, said third means comprising at least two sample-and hold circuits used for respectively sampling and holding the levels of two successive positive-going peaks corresponding to "1" in said 1010 synchronizing signal so that said control signal represents a difference between amplitudes of said two successive positive-going peaks.
Claim 3
Dependent Claim
63 words
A circuit arrangement as recited in claim 1 wherein said frequency response control means comprises amplifier means connected for receiving said PCM signal and said control signal, said amplifier means including a frequency sensitive circuit having a frequency setting component, said frequency setting component receiving said control signal for altering the frequency response of said frequency setting circuit and of said amplifier means.
Claim 4
Dependent Claim
105 words
A circuit arrangement as recited in claim 1, wherein said third means comprises at least three sample-and-hold circuits for respectively sampling and holding the levels of said two successive positive-going peaks corresponding to the first and second "1" signals of said 1010 synchronizing signal and for sampling and holding the level of a negative-going peak corresponding to the first "0" signal of said 1010 synchronizing signal, so that said control signal represents a value given by Ea'-(Eb'+Ec')/2 where Ea' and Eb' are the levels of said two successive positive-going peaks and Ec' is the level of said negative going peak of said 1010 synchronizing signal.
Claim 5
Dependent Claim
55 words
A circuit arrangement as recited in claim 3 wherein said predetermined format of said PCM signal is such that said 1010 synchronizing signal follows a pedestal level portion considerably longer than each "1" or "0" of said 1010 synchronizing signal, said pedestal level being lower than the level of "0" of said 1010 synchronizing signal.
Claim 6
Dependent Claim
209 words
A circuit arrangement for a data acquisition circuit of a PCM processor responsive to a PCM signal of a predetermined format and having a 1010 synchronizing signal and a digital signal both arranged in series of data blocks so that each 1010 synchronizing signal is followed by a corresponding data block, said circuit arrangement comprising: (a) first means responsive to bits of said 1010 synchronizing signal of said PCM signal for producing timing signals; (b) second means responsive to said timing signals for detecting positive and/or negative peak levels bf bits of only said 1010 synchronizing signal of said PCM signal; (c) third means responsive to said second means for producing a control signal representative of detected peak levels of said 1010 synchronizing signal; and (d) a frequency response control means responsive to said control signal for changing the frequency response to said PCM signal such that the frequency response to said PCM signal is controlled by said control signal which is produced using the peak levels of said 1010 synchronizing signal which immediately precedes each of said data blocks wherein said frequency response control means includes means for changing the frequency response of said PCM processor to said PCM signal as a function of said detected peak levels.
Claim 7
Dependent Claim
209 words
A circuit arrangement for a data acquisition circuit of a PCM processor responsive to a PCM signal of a predetermined format and having a 1010 synchronizing signal and a digital signal both arranged in series of data blocks so that each 1010 synchronizing signal is followed by a corresponding data block, said circuit arrangement comprising: (a) first means responsive to bits of said 1010 synchronizing signal of said PCM signal for producing timing signals; (b) second means responsive to said timing signals for detecting positive and/or negative peak levels bf bits of only said 1010 synchronizing signal of said PCM signal; (c) third means responsive to said second means for producing a control signal representative of detected peak levels of said 1010 synchronizing signal; and (d) a frequency response control means responsive to said control signal for changing the frequency response to said PCM signal such that the frequency response to said PCM signal is controlled by said control signal which is produced using the peak levels of said 1010 synchronizing signal which immediately precedes each of said data blocks wherein said frequency response control means includes means for changing the frequency response of said PCM processor to said PCM signal as a function of said detected peak levels.
Claim 8
Dependent Claim
34 words
A circuit arrangement as receited in claim 5 wherein said means for changing comprises gain changing means for changing a gain of a signal path for PCM signal components of a predetermined frequency range.
Claim 9
Dependent Claim
55 words
A circuit arrangement as recited in claim 6 wherein said gain changing means comprises means for changing a resistance in series with a capacitance in a gain circuit thereby to change, in accordance with said control signal, the gain of said gain circuit for said predetermined frequency range determined by said resistance and said capacitance.
Claim 10
Independent Claim
196 words
A method of improving the waveform of eye pattern of a PCM signal of a predetermined format and having a 100 synchronizing signal and a digital signal both arranged in series of data blocks so that each 1010 synchronizing signal is followed by each data block, said method comprising the steps of: (a) detecting bits of said 1010 synchronizing signal of said PCM signal for producing timing signals; (b) detecting positive and/or negative peak levels of bits of only said 1010 synchronizing signal of said PCM signal by using said timing signals; (c) producing a control signal using detect peak levels of said 1010 synchronizing signal; and (d) controlling the frequency response to said PCM signal such that the frequency response to said PCM signal is controlled by said control signal which is produced using the peak levels of said 1010 synchronizing signal which immediately precedes each said data block said step of producing said control signal comprising the further steps of sampling and holding the levels of two successive positive-going peaks corresponding to "1" in said 1010 synchronizing signal so that said control signal represents a difference between amplitudes of said two successive positive-going peaks.
Claim 11
Independent Claim
196 words
A method of improving the waveform of eye pattern of a PCM signal of a predetermined format and having a 100 synchronizing signal and a digital signal both arranged in series of data blocks so that each 1010 synchronizing signal is followed by each data block, said method comprising the steps of: (a) detecting bits of said 1010 synchronizing signal of said PCM signal for producing timing signals; (b) detecting positive and/or negative peak levels of bits of only said 1010 synchronizing signal of said PCM signal by using said timing signals; (c) producing a control signal using detect peak levels of said 1010 synchronizing signal; and (d) controlling the frequency response to said PCM signal such that the frequency response to said PCM signal is controlled by said control signal which is produced using the peak levels of said 1010 synchronizing signal which immediately precedes each said data block said step of producing said control signal comprising the further steps of sampling and holding the levels of two successive positive-going peaks corresponding to "1" in said 1010 synchronizing signal so that said control signal represents a difference between amplitudes of said two successive positive-going peaks.
Claim 12
Dependent Claim
57 words
A method as recited in claim 8 comprising the step of providing said predetermined format of said PCM signal such that said 1010 synchronizing signal follows a pedestal level portion considerably longer than each "1" or "0" of said 1010 synchronizing signal, said pedestal level being lower than the level of "0" of said 1010 synchronizing signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-12 | 1990-07-14 | 1991-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-12 | 1994-07-14 | 1995-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-12 | 1998-07-14 | 1999-01-13 | $7700.00 | Window Closed / Lapsed |