Semiconductor device having non-volatile storage transistors

Claim 1

A semiconductor device comprising a matrix of storage cells which are arranged in rows and columns, and a common access line for each row, each storage cell comprising a non-volatile storage transistor and a first access transistor connected in series therewith, the storage transistor having an insulated control electrode and the first access transistor having an insulated gate electrode, the gate electrodes of the first access transistors of a row of storage cells being connected to the common access line for this row, a decoder for driving the access line, the access lines being connected to said decoder for driving the access lines with selection signals, whereby the first access transistors of a selected row of storage cells are conducting and the first access transistors of the remaining rows of storage cells are non-conducting, each row of storage cells comprising at least two groups of storage cells, in each of these groups the insulated control electrodes being connected to each other and by means of a switch controllable by said common access line to a control line common to a column of groups, and each storage cell at one end of a series arrangement being connected to a first conductor common to a column of storage cells and at the other end of the series arrangement being coupled to a second conductor common to at least a column of storage cells, characterized in that in each of the storage cells in the series arrangement between the first and second conductors there is provided a second access transistor having an insulated gate electrode, the gate electrodes of the second access transistors of a row of storage cells being connected to a second access line common to this row, the decoder comprising means by which during erasing and writing in each row the first and second access lines are driven with signals complementary to each other and during reading at least in a selected row the first and second access lines are driven with signals substantially equal to each other, while in each group of storage cells the insulated control electrodes are connected by means of a switch controllable with the second common access line to a selected potential such that the potential differences occurring across the storage transistor can be limited to values which are substantially not greater than the values which can occur across the storage transistor in the reading condition.