Abstract A noise reduction circuit for reducing noise in video signal comprises delay circuits for delaying an output video signal for delay time 2S and H-S (H denotes one horizontal scanning period and S denotes a half of one period of the color subcarrier), an average circuit for averaging the outputs of the delay circuits, a subtraction circuit for subtracting the output of the average circuit from an input video signal, an attenuation circuit for attenuating the output of the subtraction circuit, an addition circuit for adding the output of the attenuation circuit to the input video signal, and an edge detection circuit for detecting the edge of pattern in the input video signal. The attenuation factor of the attenuation circuit is set into zero when the edge of pattern is detected.
Inventors
👤 Kazuhiro Kaizaki
👤 Sadao Kubota
👤 Hiroshi Harada
👤 Shigeo Matsuura
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-25 21:12
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
116 words
A noise reduction circuit comprising: a plurality of delay circuits for delaying an output video signal for different delay times respectively; an average circuit for averaging the outputs of the delay circuits; a subtraction circuit for subtracting the output of the average circuit from an input video signal; an attenuation circuit having an attenuation factor for attenuating the output of the subtraction circuit; an addition circuit for adding the output of the attenuation circuit to the input video signal; and an edge detection circuit for detecting the existence of an edge of a pattern in the input video signal; the attenuation factor of the attenuation circuit being controlled by the output of the edge detection circuit.
Claim 2
Dependent Claim
116 words
A noise reduction circuit comprising: a plurality of delay circuits for delaying an output video signal for different delay times respectively; an average circuit for averaging the outputs of the delay circuits; a subtraction circuit for subtracting the output of the average circuit from an input video signal; an attenuation circuit having an attenuation factor for attenuating the output of the subtraction circuit; an addition circuit for adding the output of the attenuation circuit to the input video signal; and an edge detection circuit for detecting the existence of an edge of a pattern in the input video signal; the attenuation factor of the attenuation circuit being controlled by the output of the edge detection circuit.
Claim 3
Dependent Claim
55 words
A noise reduction circuit according to claim 1, wherein said plurality of delay circuits is composed of a delay circuit for giving the delay time H-S and a delay circuit for giving the delay time 2S, where H denotes one horizontal scanning period and S denotes a half of one period of the color subcarrier.
Claim 4
Dependent Claim
22 words
A noise reduction circuit according to claim 2, wherein the period H is 63.5 μsec. and the period S is 0.14 μsec.