Cluster computer based education delivery system

Claim 1

An interactive instructional multi-processor system for providing instructional programs for execution at one or more processor stations while relieving memory requirements at said processor stations without allowing a perceivable delay to users at said processor stations as a result of paging of instructional program segments, comprising: a cluster subsystem and a plurality of processor stations interconnected by a high speed multi-access communication subsystem, in which said cluster subsystem comprises: at least one mass storage device for storing a library of instructional programs averaging at least about 50 kilobytes in length, high speed buffer means coupled to said mass storage device for simultaneously storing a plurality of instructional programs, an interface for said speed communication sub-system, and processor means including a digital processor for managing said mass storage device, said high speed buffer means and said interface, said processor means further including a bus interconnecting said mass storage device, said high speed buffer means, said interface and said digtal processor, said digital processing including controller means for transferring a requested instructional program from said mass storage device to said high speed buffer means and for retaining said instructional program in said high speed buffer means for at least a target time related to the plurality of processor stations coupled to said cluster subsystem, each of said processor stations comprising: a microprocessor, electronic memory of about 64 Kbytes or less and display controlled by said microprocessor, an interface for bidirectional communication coupled to and controlled by said microprocessor and coupled to said high speed communication subsystem, said high speed communication subsystem including means for supporting high speed bidirectional communication between said cluster subsystem and a plurality of said processor stations at a rate of at least one megabit per second, whereby said electronic memory at said microprocessor need not have a capacity to store an entire instructional program, rather a microprocessor can execute one of said instructional programs in segments without noticeable delay in loading an instructional program segment from said high speed buffer means for execution.

Claim 9

A method of providing interactive instructional programs at one of a plurality of processor stations comprising the steps of: (a) providing a mass storage device for storing a number of instructional programs for execution at said processor stations, (b) providing a high speed buffer memory of capacity sufficient to simultaneously store a plurality of said instructional programs, (c) providing a plurality of processor stations for executing segments of an instructional program in response to a user request, (d) providing a multi-access communication sub-system interconnecting said plurality of processor stations and said high speed buffer memory, (e) formulating a request for a specific program segment, at a processor station, in response to a user input, and communicating said request to said cluster subsystem via said mult-accoss communication sub-system, (f) responding at said cluster subsystem by extracting the requested program segment from said high speed buffer memory and transmitting said program segment to said requesting processor station via said multi-access communication sub-system.

Claim 10

A method of providing interactive instructional programs at one of a plurality of processor stations comprising the steps of: (a) providing a mass storage device for storing a number of instructional programs for execution at said processor stations, (b) providing a high speed buffer memory of capacity sufficient to simultaneously store a plurality of said instructional programs, (c) providing a plurality of processor stations for executing segments of an instructional program in response to a user request, (d) providing a multi-access communication sub-system interconnecting said plurality of processor stations and said high speed buffer memory, (e) formulating a request for a specific program segment, at a processor station, in response to a user input, and communicating said request to said cluster subsystem via said mult-accoss communication sub-system, (f) responding at said cluster subsystem by extracting the requested program segment from said high speed buffer memory and transmitting said program segment to said requesting processor station via said multi-access communication sub-system.