Fail safe protection circuitry for a commerical microprocessor in encryption equipment

Claim 1

Fail Safe protection circuitry for a commercial microprocessor in encryption equipment comprising: a first microprocessor, including instruction registers, connected to perform predetermined functions and control additional external circuitry in accordance with a specific program; a second microprocessor similar to said first microprocessor and connected to said first microprocessor for comparing bits stored in the instruction registers; a memory having the specific program stored therein and connected to said first and second microprocessors for control thereof in accordance with the stored program; and a plural phase clock connected to said first and second microprocessors causing said first microprocessor to step in response to each pulse in a first clock phase with certain instruction bits being stored in the instruction register thereof, said second microprocessor to step in response to each pulse in a second clock phase with certain instruction bits being stored in the instruction register thereof, the bits in the instruction registers of the first microprocessor to be compared to the bits in the instruction registers of the second microprocessor in response to each pulse in a third clock phase, and the instructions from one of said first and second microprocessors to be executed in response to each pulse in a fourth clock phase if a comparison occurs.