US4634895A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS peak detector and AC filter
Assignee: Nokia Bell Labs
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Filing: 1984-07-11
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Granted: 1987-01-06
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Expires: 2004-07-11
Abstract
Abstract The present invention relates to a CMOS peak detection circuit (10) which does not require a blocking diode as is used in conventional peak detection circuits. The detection circuit of the present invention comprises a comparator which functions to compare the current value of an AC input signal to a current peak value stored on a capacitor (16). The output of the comparator is connected to a NAND gate which in turn activates a CMOS transmission gate (12) disposed between the input signal line and the storage capacitor. When the current value of the input signal is greater than the current peak value stored on the capacitor, the CMOS transmission gate is turned on and the AC input signal is transferred to the storage capacitor. Alternatively, if the current value of the input signal is less than that stored on the capacitor, the NAND gate will not activate the CMOS transmission gate, and the input signal cannot pass to the capacitor. A negative peak detector can be formed merely by inverting the inputs to the comparator and resetting the storage capacitor to the positive power supply instead of the negative power supply. A tandem arrangement of a positive peak detector and a negative peak detector formed in accordance with the present invention may be utilized to determine the DC level of an AC input signal, since each detector will generate the peak positive and negative values of the input signal and the DC level is defined as the average value of these two peak values.
Inventors
- 👤 Mark Y. F. Luong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:45
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/04
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
137 words
A circuit for detecting the DC voltage level of an AC input signal, the circuit comprising positive peak detectionmeans for determining a peak positive value of the AC input signal; negative peak detection means for determining a peak negative value of said AC input signal; means for averaging the peak positive value and the peak negative value of said AC input signal to form the DC voltage level, the averaging means including a CMOS transmission gate disposed between the output of the positive peak detection means and the negative peak detection means, said transmission gate responsive to both the negative peak detection means and an external clock source for coupling together the outputs of said negative peak detection means and the positive peak detection means in response to a predetermined clock signal from said external clock source.
Claim 2
Dependent Claim
137 words
A circuit for detecting the DC voltage level of an AC input signal, the circuit comprising positive peak detectionmeans for determining a peak positive value of the AC input signal; negative peak detection means for determining a peak negative value of said AC input signal; means for averaging the peak positive value and the peak negative value of said AC input signal to form the DC voltage level, the averaging means including a CMOS transmission gate disposed between the output of the positive peak detection means and the negative peak detection means, said transmission gate responsive to both the negative peak detection means and an external clock source for coupling together the outputs of said negative peak detection means and the positive peak detection means in response to a predetermined clock signal from said external clock source.
Claim 3
Dependent Claim
314 words
A detection circuit as defined in claim 1 wherein the positive peak detection means comprises storage means for monitoring and storing a current positive peak voltage level; a comparator responsive to both the AC input signal and the current peak voltage level for comparing said AC input signal and said current peak voltage level and generating a first output when said AC input signal is greater than said current peak voltage level and generating a second output when said AC input signal is less than or equal to said current peak voltage level; and CMOS control means disposed in a signal path between said AC inut signal and said storage means and responsive to the output of the comparator for connecting said AC input signal to said storage means when said comparator produces the first output signal and disconnecting said AC input signal from said storage means when said comparator produces the second output signal; and the negative peak detection means comprises storage means for monitoring and storing a current negative peak voltage level; a comparator responsive to both said AC input signal and the current negative peak voltage level for comparing said AC input signal and said current negative peak voltage level and generating a first output when said AC input signal is less than said current negative peak voltage level and generating a second output when said AC input signal is greater than or equal to said current negative peak voltage level; and CMOS control means disposed in a signal path between said AC input signal and said negative peak storage means and responsive to the output of the comparator for connecting said AC input signal to said negative peak storage means when said negative comparator produces the first output signal and disconnecting said AC input signal from said negative peak storage means when said negative comparator produces the second output signal.
Claim 4
Dependent Claim
50 words
A detection circuit as defined in claim 2 wherein the positive peak detection storage means comprises a capacitor connected between the CMOS control means and a negative power supply and the negative peak detection storage means comprises a capacitor connected between the CMOS control means and said negative power supply.
Claim 5
Dependent Claim
122 words
A detection circuit as defined in claim 2 wherein the positive peak detection CMOS control means comprises logic means responsive to the output of the comparator for generating a first logic signal when the comparator generates its first output signal and generating a second logic signal when the comparator generates its second output signal; and a CMOS transmission gate disposed in the signal path between the input voltage signal and the storage means and responsive to the output signal generated by the logic means for connecting said input voltage signal to said storage means when the logic means generates its first output signal and disconnecting said input voltage signal from said storage means when the logic means generates its second output signal.
Claim 6
Dependent Claim
66 words
A detection circuit as defined in claim 4 wherein the logic means comprises a NAND gate responsive to both the output of the comparator and a reference signal wherein the reference signal maintains a logical "1" value such that the NAND gate produces a logical "0" as the first logic signal output and a logical "1" as the second logic signal output of said logic means.
Claim 7
Dependent Claim
122 words
A detection circuit as defined in claim 2 wherein the negative peak detection CMOS control means comprises logic means responsive to the output of the comparator for generating a first logic signal when the comparator generates its first output signal and generating a second logic signal when the comparator generates it second output signal; and a CMOS transmission gate disposed in the signal path between the input voltage signal and the storage means and responsive to the output signal generated by the logic means for connecting said input voltage signal to said storage means when the logic means generates its first output signal and disconnecting said input voltage signal from said storage means when the logic means generates its second output signal.
Claim 8
Dependent Claim
66 words
A detection circuit as defined in claim 6 wherein the logic means comprises a NAND gate responsive to both the output of the comparator and a reference signal wherein the reference signal maintains a logical "1" value such that the NAND gate produces a logical "0" as the first logic signal output and a logical "1" as the second logic signal output of said logic means.
References Cited (Backward Citations)
US3921010A
Cited
US4209717A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |