Sequence abnormality check system in programmable controller

Claim 1

A sequence abnormality check system in a programmable controller including a sequence circuit with elements, each element having an operational state and an associated logic level representative of the actual signal for the element, comprising: address setting means for providing an address for each element of the sequence circuit; an address setting table for storing the addresses provided by said address setting means and for storing the operational state corresponding to the addresses; a signal update storage table for storing the logic levels representative of the actual signals for the elements; signal update detecting means for generating an output when an operational state of an element stored in said address setting table is different from the logic level representative of the actual signal for the element; signal update writing means for writing into said signal update storage table an address and the logic level representative of the actual signal associated with the element having a differing operational state detected by said signal update detecting means, for writing a mark representing a last updated signal denoting the address as the last updated address, and for updating the differing operational state to correspond to the logic level representative of the actual signal; and display means, for displaying in response to said address means providing an address to said address setting table, the addresses and the logic levels stored in said signal update storage table, thereby checking a cause of the failure.