Series connected transistor protection circuit

Claim 2

A motor control system comprising: an electric motor which includes a stator having windings and a rotor; commutation control means, responsive to the position of said rotor relative to said stator for providing output signals; series connected transistor pairs connected between terminals of a power supply for applying electric currents to the windings of said motor; protection circuit means for each of said transistor pairs, responsive to said output signals from said commutation control means for providing delayed control signals to the associated series transistor pair which under conditions that would otherwise cause simultaneous conduction of said series connected transistors, and wherein said protection circuit operates according to a comparison of the present state of said output signals to their previous state.

Claim 3

A motor control system according to claim 1 wherein said protection circuit means includes a read only memory.

Claim 4

A motor control system according to claim 2 further comprising a source of timing signals for controlling the delay between said output signals and said control signals.

Claim 5

A motor control system according to claim 3 wherein said series connected transistor pairs include two transistors having their bases coupled to said circuit protection means, the collector of a first transistor connected to a first terminal of a power supply, the emitter of the first transistor connected to the collector of the second transistor, and the emitter of the second transmitter connected to a second terminal of said supply.

Claim 6

A motor control system according to claim 4 including at least three of said series connected transistor pairs.

Claim 7

A motor control system according to claim 5 including protection circuit means corresponding to each pair of series connected transistor pairs.

Claim 8

A protection circuit for preventing simultaneous conduction of a series connected transistor pair connected between terminals of a power supply, the series connected transistors being controlled according to output signals from a controller, comprising: a read only memory with parallel memory addressing inputs and parallel memory outputs; a set of latching circuits including a separate latching circuit associated with each of said parallel memory outputs, and being operable to provide parallel latch outputs; circuit means coupling control signals for controlling the conductive state of the transistors of said transistor pair to two of said memory addressing inputs, coupling two of said latch outputs to control the conductive state of the transistor of the transistor pair, and coupling the remaining of said latch outputs to the remaining of said memory addressing inputs, and a clock coupled to said set of latching circuits to periodically transfer input states of said latching circuits to said parallel latch outputs.

Claim 9

A protection circuit for preventing simultaneous conduction of a series connected transistor pair connected between terminals of a power supply, the series connected transistors being controlled according to output signals from a controller, comprising: a read only memory with parallel memory addressing inputs and parallel memory outputs; a set of latching circuits including a separate latching circuit associated with each of said parallel memory outputs, and being operable to provide parallel latch outputs; circuit means coupling control signals for controlling the conductive state of the transistors of said transistor pair to two of said memory addressing inputs, coupling two of said latch outputs to control the conductive state of the transistor of the transistor pair, and coupling the remaining of said latch outputs to the remaining of said memory addressing inputs, and a clock coupled to said set of latching circuits to periodically transfer input states of said latching circuits to said parallel latch outputs.

Claim 10

A protection circuit according to claim 7 wherein said read only memory is programmed to detect conditions that could cause simultaneous conduction of transistors of a transistor pair, and to provide a delay up to a predetermined number of clock counts when said simultaneous conduction conditions exist.

Claim 11

A protection circuit according to claim 8 wherein said delay is provided by a numerical stepping sequence in the program of said read only memory.