US4631662A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Scanning alarm electronic processor
Assignee: United States Department of the Navy
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Filing: 1984-07-05
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Granted: 1986-12-23
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Expires: 2004-07-05
Abstract
Abstract A scanning alarm electronic processor [hereinafter SAEP] for receiving andvaluating a predetermined number of analog signals is configured to perform, inter alia, high speed/high resolution analog computations thereon using micro-programmable methods and devices. The SAEP uses unique, parallel pipeline processing of certain functions to obtain the desired high sample rates. The SAEP is divided into two sections which contribute to its high speed performance. Each section contains the circuitry; i.e., modules, necessary to perform the algorithms for half of the predetermined number of analog signals. A common central processing unit module ties the two sections together. The SAEP operates to compute a droop compensated differential voltage for each one of the predetermined number of analog signals, to compute a weighted sum of the differential voltages, and to compare the weighted sum with an absolute value and perform an alarm evaluation.
Inventors
- 👤 Richard A. Stutler
- 👤 Jeffrey T. Harris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:42
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/05
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
311 words
A scanning alarm electronic processor (SAEP) for receiving and evaluating a predetermined number of analog signals, said SAEP being physically divided into two sections each section being configured to process halve of the predetermined number of analog signals, said SAEP comprising: a plurality of first section analog-to-digital (A/D) modules operatively connected at their inputs to half of the predetermined number of analog signals; a plurality of first section memory modules operatively connected to corresponding ones of said plurality of first section A/D modules; a plurality of first section arithmetic logic unit (ALU) modules operatively connected to corresponding ones of said plurality of first section memory modules; a plurality of first section control modules operatively connected to corresponding ones of said plurality of first section ALU modules, memory modules, and A/D modules; a plurality of second section A/D modules operatively connected at their inputs to the other half of the predetermined number of analog signals; a plurality of second section memory modules operatively connected to corresponding ones of said plurality second section of A/D modules; a plurality of second section ALU modules operatively connected to corresponding ones of said plurality of second section memory modules; a plurality of second section control modules operatively connected to corresponding ones of said plurality of second section ALU modules, memory modules, and A/D modules; said pluralities of first and second section analog-to-digital modules, memory modules, arithmetic logic units and control modules being connected to their respective preceeding input devices and succeeding output devices in pipeline fashion, and a common central processor unit (CPU) module operatively connected to both of said first and second section plurality of control modules, and operatively connected to both of said first and second section plurality of A/D modules, and ALU modules so as to coordinate the first and second sections together in a parallel pipeline fashion to increase the processing speed.
Claim 2
Dependent Claim
311 words
A scanning alarm electronic processor (SAEP) for receiving and evaluating a predetermined number of analog signals, said SAEP being physically divided into two sections each section being configured to process halve of the predetermined number of analog signals, said SAEP comprising: a plurality of first section analog-to-digital (A/D) modules operatively connected at their inputs to half of the predetermined number of analog signals; a plurality of first section memory modules operatively connected to corresponding ones of said plurality of first section A/D modules; a plurality of first section arithmetic logic unit (ALU) modules operatively connected to corresponding ones of said plurality of first section memory modules; a plurality of first section control modules operatively connected to corresponding ones of said plurality of first section ALU modules, memory modules, and A/D modules; a plurality of second section A/D modules operatively connected at their inputs to the other half of the predetermined number of analog signals; a plurality of second section memory modules operatively connected to corresponding ones of said plurality second section of A/D modules; a plurality of second section ALU modules operatively connected to corresponding ones of said plurality of second section memory modules; a plurality of second section control modules operatively connected to corresponding ones of said plurality of second section ALU modules, memory modules, and A/D modules; said pluralities of first and second section analog-to-digital modules, memory modules, arithmetic logic units and control modules being connected to their respective preceeding input devices and succeeding output devices in pipeline fashion, and a common central processor unit (CPU) module operatively connected to both of said first and second section plurality of control modules, and operatively connected to both of said first and second section plurality of A/D modules, and ALU modules so as to coordinate the first and second sections together in a parallel pipeline fashion to increase the processing speed.
Claim 3
Dependent Claim
102 words
The processor of claim 1 wherein said A/D module comprises: a plurality of relays; a corresponding plurality of sample-and-hold circuits operatively connected to said relays; an analog multiplexer operatively connected to said plurality of sample-and-hold circuits; an analog-to-digital (A/D) converter operatively connected to said analog multiplexer; and an A/D module interface latch operatively connected at its input to said A/D converter and at its output to said memory module, said plurality of relays being actuated by a relay select signal from said CPU module so as to feed the analog signal therethrough to the corresponding ones of said plurality of sample-and-hold circuits.
Claim 4
Dependent Claim
86 words
The processor of claim 2 wherein said memory module comprises: a plurality of memory chips operatively connected to said A/D module; a plurality of intervening latches operatively connected in an alternate fashion between said A/D module and said plurality of memory chips; and a plurality of memory module interface latches operatively connected at their inputs to the 0 th , 6 th and 28 th memory chip so as to pass the signal from said A/D module to said ALU module in a "bucket brigade" fashion.
Claim 5
Dependent Claim
131 words
The processor of claim 3 wherein said ALU module comprises: an adder/substractor (A/S) circuit; an A/S circuit input latch operative connected between a data bus and the input of said A/S circuit; an A/S circuit output latch operatively connected between the output of said A/S circuit and the data bus; a multiplier operatively connected to the data bus; an ALU module random access memory (RAM) operatively connected to the data bus; an ALU module read-only memory (ROM) operatively connected to the data bus; a less-than-zero detector operatively connected to the data bus; a sign fill circuit operatively connected to the data bus; a first accumulator latch operatively connected between the data bus and said CPU module; and a second accumulator latch operatively connected between the data bus and said CPU module.
Claim 6
Dependent Claim
130 words
The processor of claim 4 wherein said control module comprises: a two-phase clock generator having first and second phase outputs; a synchronization circuit being operatively connected to the first phase output of said two-phase clock generator, and being operatively connected at another input to said CPU module; an address counter operatively connected to said synchronization circuit and said CPU module; a plurality of control read-only memories (ROMs) operatively connected to the output of said address counter; and a plurality of control ROMs output latches operatively connected to the second phase output of said two-phase clock generator, the output of corresponding ones of said plurality of control ROMs and to a control bus so as to feed corresponding ones of said plurality of ALU modules, said memory and said A/D modules.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-22 | 1990-06-23 | 1990-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-22 | 1994-06-23 | 1994-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-22 | 1998-06-23 | 1998-12-23 | $7700.00 | Window Closed / Lapsed |