US4629995A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable emphasis circuit
Assignee: Sony Corp
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Filing: 1985-10-02
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Granted: 1986-12-16
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Expires: 2005-10-02
Abstract
Abstract A variable emphasis circuit comprises an operational amplifier for receiving an input signal, a modified integrator for receiving a first signal provided from the operational amplifier, and a dividing circuit for dividing the first signal to k times and 1-k times according to a control voltage. The 1-k times the first signal and a second signal provided from the modified integrator are fed back to the operational amplifier, and an output signal is formed from the second signal and the k times the first signal.
Inventors
- 👤 Masayuki Katakura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:56
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/04; H03H11/12; H03G; H03G5/00; H03G5/16; H03G5/18; H03G9/00; H03G9/02; H03G9/025; H03G9/12; H03G9/18
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
209 words
A variable emphasis circuit receiving an input signal and having a variable frequency characteristic controlled by a control signal supplied thereto, said variable emphasis circuit comprising: an operational amplifier having at least an inverting input and an output producing an output signal; integrating circuit means supplied with the output signal of said operational amplifier for producing an output signal and having a transfer function of T(S)=(ω O +S)/(m·S), where ω O is a zero angular frequency, m is a coefficient of said transfer function and S is a transform variable; dividing circuit means supplied with the output signal of said operational amplifier for dividing the same into first and second divided output signals, said control signal being supplied to said dividing circuit means for controlling a dividing ratio thereof; first adder means for adding said input signal, the output signal of said integrating circuit means and said first divided output signal of said dividing circuit means, and producing an output signal supplied to the inverting input of said operational amplifier; and second adder means for adding the output signal of said integrating circuit means and said second divided output signal of said dividing circuit means, and having an output for generating an output signal of said variable emphasis circuit.
Claim 2
Dependent Claim
209 words
A variable emphasis circuit receiving an input signal and having a variable frequency characteristic controlled by a control signal supplied thereto, said variable emphasis circuit comprising: an operational amplifier having at least an inverting input and an output producing an output signal; integrating circuit means supplied with the output signal of said operational amplifier for producing an output signal and having a transfer function of T(S)=(ω O +S)/(m·S), where ω O is a zero angular frequency, m is a coefficient of said transfer function and S is a transform variable; dividing circuit means supplied with the output signal of said operational amplifier for dividing the same into first and second divided output signals, said control signal being supplied to said dividing circuit means for controlling a dividing ratio thereof; first adder means for adding said input signal, the output signal of said integrating circuit means and said first divided output signal of said dividing circuit means, and producing an output signal supplied to the inverting input of said operational amplifier; and second adder means for adding the output signal of said integrating circuit means and said second divided output signal of said dividing circuit means, and having an output for generating an output signal of said variable emphasis circuit.
Claim 3
Dependent Claim
81 words
A variable emphasis circuit according to claim 1, wherein said integrating circuit means includes voltage-current converting circuit means connected to the output of said operational amplifier, an integrating capacitor connected to the output of said voltage-current converting circuit means and producing an output signal, multiplier means for multiplying a coefficient 1/m by the output signal of said operational amplifier and producing an output signal and adding circuit means for adding the output signals of said integrating capacitor and the multiplier means.
Claim 4
Dependent Claim
51 words
A variable emphasis circuit according to claim 1, wherein said integrating circuit means includes voltage-current converting circuit means having an output and connected to the output of said operational amplifier and a series circuit of an integrating capacitor and a resistor connected to the output of said voltage-current converting circuit means.
Claim 5
Dependent Claim
46 words
A variable emphasis circuit according to claim 3, wherein said voltage-current converting circuit means includes differential amplifier means and current mirror circuit means connected as a load circuit of said differential amplifier means, an output of said current mirror circuit being connected to said series circuit.
Claim 6
Dependent Claim
74 words
A variable emphasis circuit according to claim 1, wherein said dividing circuit means includes first and second transistors whose emitters are connected together at a first connection point, the output signal of said operational amplifier being supplied to said first connection point, said control signal being supplied to bases of said first and second transistors and the first and second divided output signals being generated at collectors of said first and second transistors, respectively.
Claim 7
Dependent Claim
100 words
A variable emphasis circuit according to claim 5, wherein said dividing circuit means further includes input differential amplifier means supplied with the output of said operational amplifier, third and fourth transistors whose emitters are connected together at a second connection point, said first and second current mirror circuit means, complementary outputs of said input differential amplifier means being connected to said first and second connection points, respectively, said first current mirror circuit means being connected between collectors of said first and third transistors, and said second current mirror circuit means being connected between collectors of said second and fourth transistors.
References Cited (Backward Citations)
US4055818A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-15 | 1990-06-16 | 1990-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-15 | 1994-06-16 | 1994-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-15 | 1998-06-16 | 1998-12-16 | $7700.00 | Window Closed / Lapsed |