Data and signaling time slot transfer and processing system for a set of multiplex lines

Claim 1

A data and signaling time slot transfer and processing system for a set of n first 2.048 Mbit/s multiplex lines with the information in each data or signaling time slot having a bit rate of 64 kbit/s, comprising m serial communication controllers, a clock, input and output registers associated with said controllers, said input registers being adapted to effect a bit rate change from 2.048 Mbit/s to 64 kbit/s and said output registers being adapted to effect a bit rate change from 64 kbit/s to 2.048 Mbit/s, a switching matrix effecting space-division switching and time-division switching and adapted to be connected on its input side to said m first multiplex lines by switching matrix input lines and to m input lines and on its output side to a set of n second multiplex lines by switching matrix output lines and to m output lines, wherein each controllers is connected to an input register and an output register, each input register has its output connected to said switching matrix by an output line, each output register has its input connected to said switching matrix by an input line, said clock has a first output adapted to supply a composite clock signal to each input and output register and a second output adapted to supply a clock signal to each controllers, said clock is adapted to supply clock signals to said switching matrix, any time slot of said first multiplex lines is connected to a fixed time slot of any output line, said output line fixed time slot is the same for all output lines, the contents of said output registers are transferred into a fixed time slot of said input lines, said input line fixed time slot is the same for all input lines, a fixed time slot of said input line is connected to any time slot of any of said switching matrix output lines, and said input and output line fixed time slots are the same.