GaAs FET oscillator noise reduction circuit

Claim 2

An improved low-noise FET oscillator comprising: (a) oscillator means having a FET device with gate and drain terminals, wherein an output signal may be derived from the drain terminal of said FET device; (b) means for driving the gate terminal of the FET oscillator circuit with a source of voltage which exhibits a low impedance at baseband frequencies. (c) means for driving the drain input of the FET oscillator circuit with a source of current which exhibits a high impedance at baseband frequencies. (d) means for maintaining the average D.C. voltage present on the drain terminal of the FET device at a relatively constant value, regardless of the average D.C. drain current, and (e) means for maintaining constant D.C. drain current at a predetermined value which corresponds to low noise oscillator operation.

Claim 3

An improved low-noise GaAs FET oscillator comprising: (a) oscillator means having a GaAs FET device with gate and drain terminals, wherein an output signal may be derived from the drain terminal of said GaAs FET device; (b) means for driving the gate terminal of the GaAs FET oscillator circuit with a source of voltage which exhibits a low impedance at baseband frequencies. (c) means for driving the drain input of the GaAs FET oscillator circuit with a source of current which exhibits a high impedance at baseband frequencies. (d) means for maintaining the average D.C. voltage present on the drain terminal of the GaAs FET device at a relatively constant value, regardless of the average D.C. drain current, and (e) means for maintaining constant D.C. drain current at a predetermined value which corresponds to low noise oscillator operation.

Claim 4

An improved low-noise GaAs FET oscillator comprising: (a) oscillator means having a GaAs FET device with gate and drain terminals, wherein an output signal may be derived from the drain terminal of said GaAs FET device; (b) means for driving the gate terminal of the GaAs FET oscillator circuit with a source of voltage which exhibits a low impedance at baseband frequencies. (c) means for driving the drain input of the GaAs FET oscillator circuit with a source of current which exhibits a high impedance at baseband frequencies. (d) means for maintaining the average D.C. voltage present on the drain terminal of the GaAs FET device at a relatively constant value, regardless of the average D.C. drain current, and (e) means for maintaining constant D.C. drain current at a predetermined value which corresponds to low noise oscillator operation.

Claim 5

The oscillator circuit of claim 1 wherein said GaAs FET oscillator means includes a GaAs FET transistor with feedback means for inducing transistor oscillation.

Claim 6

The oscillator circuit if claim 1 wherein said means for driving the gate input of the GaAs FET oscillator includes a high gain differential amplifier with high-pass negative feedback, and an adjustable voltage source.

Claim 7

The oscillator circuit of claim 1 wherein said drain terminal voltage and current maintaining means includes a voltage controlled current source which is controlled by an error amplifier whose output is dependent on the output of the voltage controlled current source.

Claim 8

A GaAs FET oscillator bias circuit for providing low noise oscillator operation, said circuit comprising: (a) current sensing means for producing a voltage related to current flow; (b) variable current source means coupled to said current sensing means having a control input for variably controlling the output current of said variable current source wherein said variable current source means is provided with a high impedance output; (c) GaAs FET oscillator means having a gate bias terminal, and a drain terminal power input coupled to the output of said current source, wherein an oscillator output signal may be derived from said drain terminal; (d) first error amplifier means having a first input coupled to a voltage reference means and a second input coupled to the output of said variable current source means, and an output coupled to the control input of said variable current source; (e) A.C. feedback means coupled between the first input of said first error amplifier means, and the output of said current sensing means; (f) second error amplifier means with a predetermined low-pass frequency response having a first input coupled to said current sensing means and a second input coupled to an adjustable voltage reference means, and an output which is D.C. coupled to the gate input of said GaAs FET oscillator.

Claim 9

A GaAs FET oscillator bias circuit for providing low noise oscillator operation, said circuit comprising: (a) current sensing means for producing a voltage related to current flow; (b) variable current source means coupled to said current sensing means having a control input for variably controlling the output current of said variable current source wherein said variable current source means is provided with a high impedance output; (c) GaAs FET oscillator means having a gate bias terminal, and a drain terminal power input coupled to the output of said current source, wherein an oscillator output signal may be derived from said drain terminal; (d) first error amplifier means having a first input coupled to a voltage reference means and a second input coupled to the output of said variable current source means, and an output coupled to the control input of said variable current source; (e) A.C. feedback means coupled between the first input of said first error amplifier means, and the output of said current sensing means; (f) second error amplifier means with a predetermined low-pass frequency response having a first input coupled to said current sensing means and a second input coupled to an adjustable voltage reference means, and an output which is D.C. coupled to the gate input of said GaAs FET oscillator.