US4626794A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplifier circuit using a P channel MOS transistor
Assignee: Toshiba Corp
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Filing: 1985-04-23
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Granted: 1986-12-02
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Expires: 2005-04-23
Abstract
Abstract In a disclosed amplifier circuit, P channel MOS transistors, as input elements, are connected at the sources to the emitters of bipolar transistors.
Inventors
- 👤 Yasuhiro Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:38
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F1/00; H03F1/08; H03F1/22; H03F1/223
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
211 words
A circuit for amplifying a differential input signal, comprising: a high potential power source terminal; a low potential power source terminal; a pair of P channel MOS transistors each having a source, a drain, and a gate, said drains being connected to said low potential power source terminal and said gates being connected to receive said differential input signal; a pair of NPN bipolar transistors each having a base, a collector, and an emitter, said emitters being connected to said sources; a base bias power source connected to said bases, said base bias power source comprising a current source having an input and an output arranged such that said input is connected to said high potential power source terminal, and a current mirror circuit having first and second inputs and first and second outputs arranged such that said first input is connected between said output of said current source and said bases, such that said second input is connected to said drains, and such that said first and second outputs are connected to said low potential power source terminal; and a pair of loads connected between said collectors and said high potential power source terminal, said collectors providing connection points for obtaining an amplified output signal representing said differential input signal.
Claim 2
Dependent Claim
211 words
A circuit for amplifying a differential input signal, comprising: a high potential power source terminal; a low potential power source terminal; a pair of P channel MOS transistors each having a source, a drain, and a gate, said drains being connected to said low potential power source terminal and said gates being connected to receive said differential input signal; a pair of NPN bipolar transistors each having a base, a collector, and an emitter, said emitters being connected to said sources; a base bias power source connected to said bases, said base bias power source comprising a current source having an input and an output arranged such that said input is connected to said high potential power source terminal, and a current mirror circuit having first and second inputs and first and second outputs arranged such that said first input is connected between said output of said current source and said bases, such that said second input is connected to said drains, and such that said first and second outputs are connected to said low potential power source terminal; and a pair of loads connected between said collectors and said high potential power source terminal, said collectors providing connection points for obtaining an amplified output signal representing said differential input signal.
Claim 3
Dependent Claim
132 words
A circuit according to claim 1, wherein said current mirror circuit comprises first and second N channel MOS transistors, each having a source, a drain, and a gate, said first N channel MOS transistor arranged such that the drain thereof is connected between the gate thereof and the drains of said pair of P channel MOS transistors and the source thereof being connected to said low potential power source terminal, said second N channel MOS transistor arranged such that the drain of said second N channel MOS transistor is connected to said output of said current source, and such that the source of said second N channel MOS transistor is connected to said low potential power source terminal, and the gates of said first and second N channel MOS transistor being interconnected.
References Cited (Backward Citations)
US4004245A
Cited
US4387309A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |