US4626707A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal selection circuit
Assignee: Hitachi Ltd
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Filing: 1984-06-04
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Granted: 1986-12-02
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Expires: 2004-06-04
Abstract
Abstract A signal selection circuit, for example, a high value selection circuit, has two unit circuit elements each including of an amplifier with an inverted input terminal and a non-inverted input terminal, and a transistor of which the base is connected to the output terminal of the amplifier and of which the emitter is connected to the inverted input terminal of the amplifier. Input signals are applied to the non-inverted input terminal of the amplifier. A constant-current circuit is connected to the emitter of npn-type transistor in each of the unit circuit elements, and is further connected to a first power-source terminal. A second power-source terminal is connected to the collector of each of the transistors.
Inventors
- 👤 Setsuo Arita
- 👤 Fumiyasu Ohkido
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:30
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/0038; G01R19/165; G01R19/16566; G01R19/16576
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
113 words
A signal selection circuit having a plurality of unit circuit elements each of which is comprised of an amplifier having an inverted input terminal and a non-inverted input terminal, and a transistor of which the base is connected to the output terminal of said amplifier and of which the emitter is connected to the inverted input terminal of said amplifier, wherein a constant-current circuit connected to a first power-source terminal is connected to the emitter of said transistor in each of said unit circuit elements, these emitters are connected to an output terminal, and the collector of said transistor in each of said unit circuit elements is connected to a second power-source terminal.
Claim 2
Dependent Claim
113 words
A signal selection circuit having a plurality of unit circuit elements each of which is comprised of an amplifier having an inverted input terminal and a non-inverted input terminal, and a transistor of which the base is connected to the output terminal of said amplifier and of which the emitter is connected to the inverted input terminal of said amplifier, wherein a constant-current circuit connected to a first power-source terminal is connected to the emitter of said transistor in each of said unit circuit elements, these emitters are connected to an output terminal, and the collector of said transistor in each of said unit circuit elements is connected to a second power-source terminal.
Claim 3
Dependent Claim
14 words
A signal selection circuit according to claim 1, wherein said transistors are npn-type transistors.
Claim 4
Dependent Claim
14 words
A signal selection circuit according to claim 1, wherein said transistors are pnp-type transistors.
Claim 5
Dependent Claim
18 words
A signal selection circuit according to claim 1, wherein said constant-current circuit is a current mirror-type constant-current circuit.
Claim 6
Dependent Claim
347 words
A signal selection circuit comprising three first selection means each receiving two input signals selected from among three input signals, said two input signals to each of said three first selection means being selected in different combinations, and each selecting and producing one signal out of said different combinations of two input signals, and a second selection means which receives signals produced by each of said first selection means; wherein, each of said first selection means has a pair of first unit circuit elements each comprised of an amplifier with an inverted input terminal and a non-inverted input terminal to receive one of said input signals, and a first transistor of which the base is connected to the output terminal of said first amplifier and of which the emitter is connected to said inverted terminal of said first amplifier, wherein a first constant-current circuit connected to a first power-source terminal is connected to the emitter of said first transistor in each of said first unit circuit elements, these emitters are connected together to form an output terminal, and the collector of said first transistor in each of said first unit circuit elements is connected to a second power-source terminal; and said second selection means has three second unit circuit elements each comprised of a second amplifier with an inverted input terminal and a non-inverted input terminal connected to said output terminal of said first selection means, and a second transistor having collector, base and emitter of conductivity types different from those of said first transistor, the base of said second transistor being connected to the output terminal of said second amplifier, and the emitter thereof being connected to the inverted input terminal of said second amplifier, and wherein a second constant-current circuit connected to said second power-source terminal is connected to the emitter of said second transistor in each of said second unit circuit elements, these emitters are connected together to form an output terminal, and the collector of said second transistor in each of said second unit circuit elements is connected to said first power-source terminal.
Claim 7
Dependent Claim
347 words
A signal selection circuit comprising three first selection means each receiving two input signals selected from among three input signals, said two input signals to each of said three first selection means being selected in different combinations, and each selecting and producing one signal out of said different combinations of two input signals, and a second selection means which receives signals produced by each of said first selection means; wherein, each of said first selection means has a pair of first unit circuit elements each comprised of an amplifier with an inverted input terminal and a non-inverted input terminal to receive one of said input signals, and a first transistor of which the base is connected to the output terminal of said first amplifier and of which the emitter is connected to said inverted terminal of said first amplifier, wherein a first constant-current circuit connected to a first power-source terminal is connected to the emitter of said first transistor in each of said first unit circuit elements, these emitters are connected together to form an output terminal, and the collector of said first transistor in each of said first unit circuit elements is connected to a second power-source terminal; and said second selection means has three second unit circuit elements each comprised of a second amplifier with an inverted input terminal and a non-inverted input terminal connected to said output terminal of said first selection means, and a second transistor having collector, base and emitter of conductivity types different from those of said first transistor, the base of said second transistor being connected to the output terminal of said second amplifier, and the emitter thereof being connected to the inverted input terminal of said second amplifier, and wherein a second constant-current circuit connected to said second power-source terminal is connected to the emitter of said second transistor in each of said second unit circuit elements, these emitters are connected together to form an output terminal, and the collector of said second transistor in each of said second unit circuit elements is connected to said first power-source terminal.
Claim 8
Dependent Claim
22 words
A signal selection circuit according to claim 5, wherein said first transistors are npn-type transistors, and said second transistors are pnp-type transistors.
Claim 9
Dependent Claim
22 words
A signal selection circuit according to claim 5, wherein said first transistors are pnp-type transistors, and said second transistors are npn-type transistors.
Claim 10
Dependent Claim
20 words
A signal selection circuit according to claim 5, wherein said frist and second constant-current circuits are current mirror-type constant-current circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |