US4626706A
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Digital signal level translation/master-slave flip flop with look-ahead
Assignee: Advanced Micro Devices Inc
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Filing: 1984-05-24
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Granted: 1986-12-02
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Expires: 2004-05-24
Abstract
Abstract Disclosed is a digital signal translation circuit for translating a first type signal to a second type signal which comprises a master latch and a slave latch. The master latch latches the incoming first type signal during a first portion of the clock signal. A slave latch latches the master latch output and generates a differential output. The differential output of the slave drives an output driver circuit which generates the second type signal.
Inventors
- 👤 Michael Allen
- 👤 Tsen-Shau Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:32
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/289
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
137 words
An apparatus for translating a first type signal to a second type signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for receiving and latching the first type signal during a portion of the clock signal and for generating a master latch signal corresponding to the level of the first type signal; (b) slave latch means for receiving and latching the master latch signal and for generating a slave latch signal; (c) lookahead means, receiving and responding to the master latch signal, for switching the slave latch signal to a state corresponding to the state of the master latch signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means, receiving and responding to the slave latch signal, for supplying the second type signal.
Claim 2
Independent Claim
137 words
An apparatus for translating a first type signal to a second type signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for receiving and latching the first type signal during a portion of the clock signal and for generating a master latch signal corresponding to the level of the first type signal; (b) slave latch means for receiving and latching the master latch signal and for generating a slave latch signal; (c) lookahead means, receiving and responding to the master latch signal, for switching the slave latch signal to a state corresponding to the state of the master latch signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means, receiving and responding to the slave latch signal, for supplying the second type signal.
Claim 3
Dependent Claim
132 words
The apparatus of claim 1, wherein: said slave latch signal is a differential slave latch signal, the differential slave latch signal including a first voltage signal and a second voltage signal and having a first state when the first voltage signal is higher than the second voltage signal and having a second state when the second voltage signal is higher than the first voltage signal, and said output driver means includes a pair of coupled transistors, one of said pair of coupled transistors receiving said first voltage signal and being turned on when the differential slave latch signal is in the first state and the other of said pair of coupled transistors receiving said second voltage signal and being turned on when the differential slave latch signal is in the second state.
Claim 4
Dependent Claim
26 words
The apparatus of claim 2, including: biasing means for biasing to a minimum level said first and second voltage signals of said differential slave latch signal.
Claim 5
Independent Claim
200 words
An apparatus for translating a first type digital to a corresponding second type digital signal, the apparatus being responsive to a clock signal, comprising; (a) master latch means for receiving and latching the first type digital signal durlng a portion of the clock signal and for generating a master latch signal corresponding to the level of the first type digital signal; (b) slave latch means, for receiving and latching said master latch signal and for generating a differential slave latch signal, the differential slave latch signal including a first voltage signal and a second voltage signal and having a first state when the first voltage signal is higher than the second voltage signal and having a second state when the second voltage signal is higher than the first voltage signal, the state of the differential slave latch signal corresponding to the first type digital signal; (c) lookahead means, receiving and responding to the master latch signal, for switching the state of the differential slave latch signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means receiving and responding to the differential slave latch signal, for supplying the second type digital signal.
Claim 6
Independent Claim
200 words
An apparatus for translating a first type digital to a corresponding second type digital signal, the apparatus being responsive to a clock signal, comprising; (a) master latch means for receiving and latching the first type digital signal durlng a portion of the clock signal and for generating a master latch signal corresponding to the level of the first type digital signal; (b) slave latch means, for receiving and latching said master latch signal and for generating a differential slave latch signal, the differential slave latch signal including a first voltage signal and a second voltage signal and having a first state when the first voltage signal is higher than the second voltage signal and having a second state when the second voltage signal is higher than the first voltage signal, the state of the differential slave latch signal corresponding to the first type digital signal; (c) lookahead means, receiving and responding to the master latch signal, for switching the state of the differential slave latch signal before said slave latch means completes a latch of the master latch signal; and (d) output driver means receiving and responding to the differential slave latch signal, for supplying the second type digital signal.
Claim 7
Dependent Claim
100 words
The apparatus of claim 4, wherein said output driver means includes: a pair of coupled transistors, one of said pair of coupled transistors respectively receiving said first voltage signal of said differential slave latch signal and being turned on when the differential slave latch signal is in the first state and the other of said pair of coupled transistors respectively receiving said second voltage signal of said differential slave latch signal and being turned on when the differential slave latch signal is in the second state, and a constant current source supplying bias current through said pair of coupled transistors.
Claim 8
Dependent Claim
36 words
The apparatus of claim 4, wherein: said pair of coupled transistor are bipolar devices having emitters connected to a common emitter node, and said constant current source supplying said bias current thorugh said common emitter node.
Claim 9
Dependent Claim
62 words
The apparatus of claim 4, including: a first voltage divider means coupled to said slave latch means for receiving said first voltage signal and for biasing said first voltage signal to a minimum level; and a second voltage divider coupled to said slave latch means for receiving said second voltage signal and for biasing said second voltage singal to a minimum level.
Claim 10
Dependent Claim
54 words
The apparatus of claim 4, wherein said slave latch means include: a first semiconductor switch and a second semiconductor switch and wherein the difference in voltage between the first voltage signal and the second voltage signal is determined by the difference in voltage drop across said first semiconductor switch and said second semiconductor switch.
Claim 11
Dependent Claim
77 words
The apparatus of claim 8, wherein said first and second semiconductor switches each include a first circuit path energized when said respective semiconductor switch is on and a second circuit path energized when said respective semiconductor switch is off, and said first circuit paths of said first and second semiconductor switches include means for increasing the voltage drop in said first circuit paths to maintain a desired difference in voltage across said first and second semiconductor switches.
Claim 12
Dependent Claim
136 words
The apparatus of claim 4, wherein said lookahead means includes: first diode means for signal coupling between the first voltage signal of said differential slave latch signal and the master latch signal to pull the first voltage signal of said differential slave latch signal to a level below the second voltage signal of the differential slave latch signal when the master latch signal indicates one level of the first type digital signal; and second diode means for signal coupling between the second voltage signal of the differential slave latch signal and the master latch signal to pull down the second voltage signal of the differential slave latch signal below the level of the first voltage signal of the differential slave latch signal when the master latch signal indicates another level of the first type digital signal.
Claim 13
Independent Claim
272 words
An apparatus for storing a TTL signal and providing a corresponding ECL signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for receiving and latching the TTL signal during a portion of the clock signal and for generating a differential master latch signal including a first master voltage signal and a second master voltage signal and having a first master state when the first master voltage signal is higher than the second master voltage signal and having a second master state when the second master voltage signal is higher than the first master voltage signal, the first and second master state of the differential master latch signal corresponding to the TTL signal; (b) slave latch means, for receiving and latching the differential master latch signal to store the TTL signal and for generating a differential slave latch signal, the differential slave latch signal including a first slave voltage signal and a second slave voltage signal and having a first slave state when the first slave voltage signal is higher than the second slave voltage signal and having a second slave state when the second slave voltage signal is higher than the first slave voltage signal, the first and second slave state of the differential slave latch signal corresponding to the TTL signal; (c) lookahead means, receiving and responding to the differeintal master latch signal, for switching the state of the differential slave latch signal before said slave latch means completes a latch of the differential master latch signal; and (d) output driver means, receiving and responding to the differential slave latch signal, for supplying the ECL signal.
Claim 14
Independent Claim
272 words
An apparatus for storing a TTL signal and providing a corresponding ECL signal, the apparatus being responsive to a clock signal, comprising: (a) master latch means for receiving and latching the TTL signal during a portion of the clock signal and for generating a differential master latch signal including a first master voltage signal and a second master voltage signal and having a first master state when the first master voltage signal is higher than the second master voltage signal and having a second master state when the second master voltage signal is higher than the first master voltage signal, the first and second master state of the differential master latch signal corresponding to the TTL signal; (b) slave latch means, for receiving and latching the differential master latch signal to store the TTL signal and for generating a differential slave latch signal, the differential slave latch signal including a first slave voltage signal and a second slave voltage signal and having a first slave state when the first slave voltage signal is higher than the second slave voltage signal and having a second slave state when the second slave voltage signal is higher than the first slave voltage signal, the first and second slave state of the differential slave latch signal corresponding to the TTL signal; (c) lookahead means, receiving and responding to the differeintal master latch signal, for switching the state of the differential slave latch signal before said slave latch means completes a latch of the differential master latch signal; and (d) output driver means, receiving and responding to the differential slave latch signal, for supplying the ECL signal.
Claim 15
Dependent Claim
122 words
The apparatus df claim 11, wherein said output driver means includes: a pair of coupled transistors, each receiving a respective one of said first and second slave voltage signals of said differential slave latch signal, one of said pair of coupled transistors being turned on when the differential slave latch signal is in the first slave state and the other of said pair of coupled transistors being turned on when the differntial slave latch signal is in the second slave state; a current source connected to said pair of coupled transistor for supplying bias current through said pair of coupled transistors; and an emitter follower output driver circuit connected to one of said pair of coupled transistors for providing the ECL signal.
Claim 16
Dependent Claim
88 words
The apparatus of claim 11, including: a first voltage divider means, receiving the first voltage signal for the differential slave latch signal and coupled to said slave latch means, for biasing the first slave voltage signal of the differential slave latch signal to a minimum level; and a second voltage divider means, receiving the second slave voltage signal of the differential slave latch signal and coupled to said slave latch means, for biasing the second slave voltage signal of the differential slave latch signal to a minimum level.
Claim 17
Dependent Claim
15 words
The apparatus of claim 11, wherein: said apparatus is fabricated on a single semiconductor chip.
Claim 18
Dependent Claim
42 words
The apparatus of claim 1 wherein: said lookahead means comprises coupling means for coupling the master latch signal to the slave latch signal, said second type of signal switches before said slave latch means completes a latch of the master latch signal.
Claim 19
Dependent Claim
155 words
The apparatus of claim 11, wherein said lookahead means includes: first diode means for signal coupling between the first slave voltage signal of said differential slave latch signal and the first master voltage signal of the differential master latch signal to pull down the first slave voltage signal of said differential slave latch signal to a level below the second slave voltage signal of the differnetial slave latch signal when the differential master latch signal indicates one level of the TTL signal; and second diode means for signal coupling between the second slave voltage signal of the differential slave latch signal and the second master voltage signal of the differential master latch signal to pull down the second slave voltage signal of the differential slave latch signal below the level of the first slave voltage signal of the differential slave latch signal when the differential master latch signal indicates another level of the TTL signal.
References Cited (Backward Citations)
US3430070A
Cited
JPS56117427A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |