Data available indicator for an exhausted operand string

Claim 1

In a data processor, which executes a predetermined instruction on a predetermined operand as indicated by an instruction word, said operand being a variable length data string made up of at least one computer word, the execution of the instruction being performed by said data processor in a sequential series of steps wherein at least one step is performed in a predetermined time period, said time period being a cycle of said data processor, and wherein at least one cycle is required to read said operand stored in a memory device of said data processor, said memory device having a plurality of addressable locations, said variable length data string being temporarily stored in at least one addressable location of said memory device, said data processor further including an apparatus for providing a control signal to indicate the end of the variable length data string thus inhibiting further reads of the variable length data string without inhibiting the subsequent steps of the cycles associated with the execution of the instruction thereby allowing the execution of the instruction to complete, said apparatus comprising: (a) memory means, having a plurality of addressable locations, each of said pluraity of addressable locations corresponding to a respective addressable location of said memory device, for storing information to generate said control signal when the stored information indicates the corresponding addressable location of the memory device is the last computer word of the variable length data string; and (b) register means for temporarily storing a read address value, said register means having an input terminal adapted to receive the read address value, the read address value corresponding to an addressable location of said memory device containing the computer word of the variable length data string to be read in the execution of the instruction, said register means further having a strobe input terminal operatively connected to said memory means whereby said control signal is operatively coupled to said register means to control the loading of an updated read address value into said register means in response to said control signal.