Synthetic speech speed control in an electronic cash register

Claim 2

A synthetic speech generation control system comprising: buffer memory means for temporarily storing speech data representative of audible speech; a synthetic speech generation circuit, receiving said speech data from said buffer memory means and converting said speech data into audible speech; write control means, operatively connected to said buffer memory means, for introducing the speech data into said buffer memory means at a selected writing speed; read control means for controlling the read out of said speech data stored in said buffer memory at a selected reading speed and the application of said speech data to said synthetic speech generation circuit; determination means for monitoring the writing speed of said write control means and the reading speed of said read control means, and for developing a control signal when said writing speed is faster than said reading speed; and control means, responsive to said control signal developed by said determination means, for increasing the reading speed of said read control means when said control signal is developed from said determination circuit.

Claim 3

The synthetic speech generation control system of claim 1, wherein said buffer memory means includes a predetermined number of memory sections, each memory section storing syllable information of said speech data.

Claim 4

The synthetic speech generation control system of claim 2, wherein said determination means comprises: first counter means for counting the number of syllables of the speech data introduced into said buffer memory means by said write control means; second counter means for counting the number of syllables of speech data read out from said buffer memory means by said read control means; and comparing means, responsive to the contents of said first and second counter means, for comparing the contents stored in said first and second counter means and for developing said control signal when the count difference is greater than a preselected number.

Claim 5

An electronic cash register including a synthetic speech generation system comprising: key input means for introducing numeral data and operation commands into said electronic cash register; central processor means, responsive to said numeral data introduced by said key input means, for conducting an arithmetic calculation on said numeral data; buffer memory means for temporarily storing speech data developed from said central processor means representative of audible speech; a synthetic speech generation circuit, receiving said speech data from said buffer memory means and converting said speech data into audible speech; write control means, operatively connected to said buffer memory means, for writing the speech data developed by said central processor means into said buffer memory means at a selected writing speed; read control means for controlling the sequential read out of said speech data stored in said buffer memory means and for applying said speech data to said synthetic speech generation circuit at a selected reading speed; first storage means for storing a signal representative of a writing condition indicative of the speed with which data is written into said buffer memory under control of said write control means; second storage means for storing a signal representative of a writing condition indicative of the speed with which data is read out of said buffer memory under control of said read control means; and synthetic speech speed control means, responsive to the signals stored in said first and second storage means, for varying the speed of the speech generation conducted by said synthetic speech generation circuit.

Claim 6

An electronic cash register including a synthetic speech generation system comprising: key input means for introducing numeral data and operation commands into said electronic cash register; central processor means, responsive to said numeral data introduced by said key input means, for conducting an arithmetic calculation on said numeral data; buffer memory means for temporarily storing speech data developed from said central processor means representative of audible speech; a synthetic speech generation circuit, receiving said speech data from said buffer memory means and converting said speech data into audible speech; write control means, operatively connected to said buffer memory means, for writing the speech data developed by said central processor means into said buffer memory means at a selected writing speed; read control means for controlling the sequential read out of said speech data stored in said buffer memory means and for applying said speech data to said synthetic speech generation circuit at a selected reading speed; first storage means for storing a signal representative of a writing condition indicative of the speed with which data is written into said buffer memory under control of said write control means; second storage means for storing a signal representative of a writing condition indicative of the speed with which data is read out of said buffer memory under control of said read control means; and synthetic speech speed control means, responsive to the signals stored in said first and second storage means, for varying the speed of the speech generation conducted by said synthetic speech generation circuit.

Claim 7

The electronic cash register of claim 4, wherein said buffer memory means includes a predetermined number of memory sections, each memory section storing syllable information of said speech data.

Claim 8

The electronic cash register of claim 5, wherein said first storage means stores an address number of said memory section to which the next syllable information should be introduced, and said second storage means stores an address number of said memory section from which the next syllable information should be read out.

Claim 9

The electronic cash register of claim 6, wherein said first storage means include a pointer, and said second storage means include another pointer.

Claim 10

The electronic cash register of claim 6, wherein said synthetic speech speed control means comprises: a subtractor subtracting the address number stored in said second storage means from the address number stored in said first storage means to develop a subtraction result signal; first determination means, responsive to the subtraction result signal developed by said subtractor, for determining whether the subtraction result obtained by said subtractor is greater than a first predetermined value to develop an affirmative determination signal; and first control signal developing means for developing a first control signal when an affirmative determination signal is developed by said first determination means, said first control signal being applied to said synthetic speech generation circuit so as to increase the speed of the synthetic speech generation operation.

Claim 11

The electronic cash register of claim 8, wherein said synthetic speech speed control means further comprises: second determination means, responsive to the subtraction result signal developed by said subtractor, for determining whether the subtraction result obtained by said subtractor is smaller than a second predetermined value, said second predetermined value being less than said first predetermined value; and second control signal developing means for developing a second control signal when an affirmative determination signal is obtained by said second determination circuit, said second control signal being applied to said synthetic speech generation circuit so as to decrease the speed of the speech generation operation.

Claim 12

An electronic cash register including a synthetic speech generation system comprising: key input means for introducing numeral data and operation commands into said electronic cash register; central processor means, responsive to said numeral data introduced by said key input means, for conducting an arithmetic calculation on said numeral data; buffer memory means for temporarily storing speech data developed from said central processor means representative of audible speech; a synthetic speech generation circuit, receiving said speech data from said buffer memory means and converting said speech data into audible speech; write control means, operatively connected to said buffer memory means, for writing the speech data developed by said central processor means into said buffer memory means at a selected writing speed; read control means for controlling the sequential read out of said speech data stored in said buffer memory means and for applying said speech data to said synthetic speech generation circuit at a selected reading speed; first storage means for storing a signal representative of a writing condition indicative of the speed into which data is written into said buffer memory under control of said write control means; second storage means for storing a signal representative of a writing condition indicative of the speed with which data is read out of said buffer memory under control of said read control means; and key input control means for disabling said key input means in response to the signals stored in said first and second storage means.

Claim 13

An electronic cash register including a synthetic speech generation system comprising: key input means for introducing numeral data and operation commands into said electronic cash register; central processor means, responsive to said numeral data introduced by said key input means, for conducting an arithmetic calculation on said numeral data; buffer memory means for temporarily storing speech data developed from said central processor means representative of audible speech; a synthetic speech generation circuit, receiving said speech data from said buffer memory means and converting said speech data into audible speech; write control means, operatively connected to said buffer memory means, for writing the speech data developed by said central processor means into said buffer memory means at a selected writing speed; read control means for controlling the sequential read out of said speech data stored in said buffer memory means and for applying said speech data to said synthetic speech generation circuit at a selected reading speed; first storage means for storing a signal representative of a writing condition indicative of the speed into which data is written into said buffer memory under control of said write control means; second storage means for storing a signal representative of a writing condition indicative of the speed with which data is read out of said buffer memory under control of said read control means; and key input control means for disabling said key input means in response to the signals stored in said first and second storage means.

Claim 14

The electronic cash register of claim 10, wherein said buffer memory means includes a predetermined number of memory sections, each memory section storing syllable information of said speech data.

Claim 15

The electronic cash register of claim 11, wherein said first storage means includes a pointer for storing an address number of said memory section to which the next syllable information should be introduced, and said second storage means includes another pointer for storing an address number of said memory section from which the next syllable information should be read out.

Claim 16

The electronic cash register of claim 12, wherein said key input control means comprises: a subtractor subtracting the address number stored in said second storage means from the address number stored in said first storage means to develop a subtraction result signal; determination means for determining whether the subtraction result obtained by said subtractor is greater than a preselected value to develop an affirmative determination signal; control signal developing means for developing a control signal when the affirmative determination signal is developed by said determination means; and means, responsive to said control signal developed by said control signal developing means, for disconnecting said key input means from said central processor means.