Adjustable time delay circuit

Claim 2

An adjustable time delay circuit (10) which includes an adjustment feature compensating for environmental influences comprising: an input terminal (14); an output terminal (41); a plurality of serially connected time delay elements (16) forming a tapped time delay line (12), said time delay line having one end thereof connected to the input terminal; first means (52) for generating first signal (A), said first signal being fed to the input terminal of said time delay line (12); second means (56) for generating second signal (C) in response to said first signal; third means (22e-m) responsive to said first signal at a plurality of selected locations along said time delay line (12) and responsive to said second signal for providing one of a plurality of possible control signals in response to a predetermined relationship between said first (A) and second (C) signals; and a plurality of signal activated switches (36e-m), each switch being responsive to a corresponding one of said control signals for connecting a selected tap (38e-m) of said time delay line (12) to said output terminal (41).

Claim 3

An adjustable time delay circuit (10, 50) including a plurality of components having signal propagation characteristics which are effected by environmental conditions comprising: a plurality of serially connected time delay elements (16) forming a tapped time delay line (12); first means (52) for generating first signal (A), said first means (52) for generating said first signal being connected to an input of said time delay line (12); second means (56) for generating second signal (C) in response to said first signal; means (22e-m) responsive to said first signal (A) at selected taps (20e-m) of said time delay line (12) and to said second signal (C) for providing one of a plurality of control signals in response to a predetermined relationship between the first signal (A) appearing at the selected tap and said second signal (C); and a plurality of switches (36e-m), each switch having approximately the same signal propagation characteristics and each being responsive to a corresponding one of said control signals for switching a selected tap of said time delay line (12) through a selected one of said switches (36e-m) to an output terminal (41), the propagation characteristics through the selected one of said switches (36e-m) and said time delay line (12) providing a predetermined time delay to signals passing therethrough.

Claim 4

An adjustable time delay circuit (10, 50) including a plurality of components having signal propagation characteristics which are effected by environmental conditions comprising: a plurality of serially connected time delay elements (16) forming a tapped time delay line (12); first means (52) for generating first signal (A), said first means (52) for generating said first signal being connected to an input of said time delay line (12); second means (56) for generating second signal (C) in response to said first signal; means (22e-m) responsive to said first signal (A) at selected taps (20e-m) of said time delay line (12) and to said second signal (C) for providing one of a plurality of control signals in response to a predetermined relationship between the first signal (A) appearing at the selected tap and said second signal (C); and a plurality of switches (36e-m), each switch having approximately the same signal propagation characteristics and each being responsive to a corresponding one of said control signals for switching a selected tap of said time delay line (12) through a selected one of said switches (36e-m) to an output terminal (41), the propagation characteristics through the selected one of said switches (36e-m) and said time delay line (12) providing a predetermined time delay to signals passing therethrough.

Claim 5

The adjustable time delay circuit (10, 50) of claim 2 wherein the environmental influences on said time delay line (12) after the electrical characteristics of the time delay line (12) in a manner similar to the alteration of the electrical characteristics of the switch (36e-m) in response to the same environmental influences.

Claim 6

The adjustable time delay circuit (10, 50) of claim 3 which provides a nominal time delay condition at a selected tap (38h) along said time delay line (12), a selected one of said switches selects a tap (38e-m) introducing a greater portion of the time delay line (12) in response to said predetermined relationship occurring at a location on said time delay line (12) subsequent to said selected nominal tap (38h).

Claim 7

The adjustable time delay circuit (10, 50) of claim 4 wherein said control signal generating means (22e-m) includes a plurality of gates, one input of each of said gates is connected to said second signal generating means (56) for receiving said second signal (C), and the second input of said means (22e-m) is connected to a selected one of the taps (38e-m) along said time delay line (12).

Claim 8

The adjustable time delay circuit (10, 50) of claim 5 wherein each of said switches (36e-m) includes means (30e-m), (32f-m) for disabling those switches (36e-m) controlled by a control signal generated in response to subsequent delay line conditions.

Claim 9

The adjustable time delay circuit (10, 50) of claim 6 wherein said first generating means includes a clock (52) having first and second edge transitions, means (56) for detecting said first edge transition and generating a short duration pulse (B) providing said second signal (C).

Claim 10

An adjustable time delay circuit (10, 50) comprising: a time delay line (12) having an input terminal (14) and a plurality of output connections (38e-m) and providing time delays to signals passing from said input terminal (14) to said output connections (38e-m), said time delay line comprising a plurality of serially connected inverters (16), selected inverter connections (20e-m) providing sampling taps; first and second means (52, 56) for generating first and second time related signals, said first signal means (52) being connected to the input terminal (14) of said time delay line (12); a plurality of first logic gates (22e-m) equal in number to the number of sampling taps (20e-m), one input of each of said first logic gates (22e-m) connected to a corresponding one of said sampling taps (20e-m), and a second input of each of said first logic gates (22e-m) connected to said second signal generating means (56), the output of each of said first logic gates (22e-m) providing a third signal in response to a predetermined relationship between the first and second signals (A, C) at the corresponding inputs of said first logic gates (22e-m); a plurality of flip-flops (30e-m), one input of each flip-flop (30e-m) being connected to a corresponding output of one of said first logic gates (22e-m); a plurality of second logic gates (32f-m) ,the number of said second logic gates (32f-m) being one less than the number of said flip-flops (30e-m) and corresponding respectively to all but the first flip-flop (30e) and one input of each of said second logic gates (32f-m) is connected to the output of a corresponding one of said flip-flops (30f-m), one output of each flip-flop (30g-m) being connected to an input of all second logic gates (32f-m) subsequent to said second logic gates (32f-m) corresponding to the flip-flop (30f-m) so that a selected flip-flop (30f-m) will inhibit all second logic gates (32f-m) corresponding to flip-flops (30e-m) controlled by first logic gates (22e-m) connected to subsequent sampling taps (20e-m) along said time delay line (12); a plurality of third logic gates (34e-m) equal in number to said flip-flops (30e-m), one input of a first one (34e) of said third logic gates being connected to the output of a corresponding first one of said flip-flops (30e) and one input of each of the remaining third logic gates (30f-m) being connected to the output of each of said second logic gates (32f-m), a second input of each of said third logic gates (34e-m) being connected to one of said output connections (38e-m); and a fourth logic gate (40), having multiple inputs, with each input of said fourth logic gate (40) being connected to the output of one of said third logic gates (34e-m) so that, in response to a predetermined relationship between said first and second signals (A, C) at a first one of said first logic gates (22e-m), said corresponding flip-flop (30e-m) will be controlled by said third signal thereby inhibiting all subsequent second logic gates (32f-m) and causing the signal at the corresponding signal connection connected to the input of the corresponding third logic gate (34e-m) to pass therethrough and through said fourth logic gate (40).

Claim 11

An adjustable time delay circuit (10, 50) comprising: a time delay line (12) having an input terminal (14) and a plurality of output connections (38e-m) and providing time delays to signals passing from said input terminal (14) to said output connections (38e-m), said time delay line comprising a plurality of serially connected inverters (16), selected inverter connections (20e-m) providing sampling taps; first and second means (52, 56) for generating first and second time related signals, said first signal means (52) being connected to the input terminal (14) of said time delay line (12); a plurality of first logic gates (22e-m) equal in number to the number of sampling taps (20e-m), one input of each of said first logic gates (22e-m) connected to a corresponding one of said sampling taps (20e-m), and a second input of each of said first logic gates (22e-m) connected to said second signal generating means (56), the output of each of said first logic gates (22e-m) providing a third signal in response to a predetermined relationship between the first and second signals (A, C) at the corresponding inputs of said first logic gates (22e-m); a plurality of flip-flops (30e-m), one input of each flip-flop (30e-m) being connected to a corresponding output of one of said first logic gates (22e-m); a plurality of second logic gates (32f-m) ,the number of said second logic gates (32f-m) being one less than the number of said flip-flops (30e-m) and corresponding respectively to all but the first flip-flop (30e) and one input of each of said second logic gates (32f-m) is connected to the output of a corresponding one of said flip-flops (30f-m), one output of each flip-flop (30g-m) being connected to an input of all second logic gates (32f-m) subsequent to said second logic gates (32f-m) corresponding to the flip-flop (30f-m) so that a selected flip-flop (30f-m) will inhibit all second logic gates (32f-m) corresponding to flip-flops (30e-m) controlled by first logic gates (22e-m) connected to subsequent sampling taps (20e-m) along said time delay line (12); a plurality of third logic gates (34e-m) equal in number to said flip-flops (30e-m), one input of a first one (34e) of said third logic gates being connected to the output of a corresponding first one of said flip-flops (30e) and one input of each of the remaining third logic gates (30f-m) being connected to the output of each of said second logic gates (32f-m), a second input of each of said third logic gates (34e-m) being connected to one of said output connections (38e-m); and a fourth logic gate (40), having multiple inputs, with each input of said fourth logic gate (40) being connected to the output of one of said third logic gates (34e-m) so that, in response to a predetermined relationship between said first and second signals (A, C) at a first one of said first logic gates (22e-m), said corresponding flip-flop (30e-m) will be controlled by said third signal thereby inhibiting all subsequent second logic gates (32f-m) and causing the signal at the corresponding signal connection connected to the input of the corresponding third logic gate (34e-m) to pass therethrough and through said fourth logic gate (40).

Claim 12

An adjustable time delay circuit (10, 50) including an adjustment feature compensating for environmental influences of components comprising the time delay circuit which environmental influences affect propagation characteristics of data signals passing through the time delay circuit, said circuit comprising: an input terminal (14); an output terminal (41); a plurality of serially connected time delay elements (16) forming a tapped time delay line (12), said time delay line having one end thereof connected to the input terminal; a data input terminal (64) for accepting incoming data signals; means (54) for connecting said terminal (64) to said input terminal (14); means (52) for generating a first signal (A); means (56) for generating a second signal (C) in response to said first signal; means (60) responsive to said incoming data signals for generating a control signal (F); said means (54) responsive to said control signal (F) for disconnecting said data input terminal (64) and connecting said first signal (A) to the input terminal (14); means (22e-m) responsive to said first signal (A) at a plurality of selected locations along said time delay line (12) and responsive to said second signal (C) for providing one of a plurality of possible control signals in response to a predetermined relationship between said first (A) and said (C) signals; and a plurality of signal activated switches (36e-m), each switch being responsive to a corresponding one of said control signals for connecting a said selected tap (38e-m) of said time delay line (12) to said output terminal (41).

Claim 13

An adjustable time delay circuit (10, 50) including an adjustment feature compensating for environmental influences of components comprising the time delay circuit which environmental influences affect propagation characteristics of data signals passing through the time delay circuit, said circuit comprising: an input terminal (14); an output terminal (41); a plurality of serially connected time delay elements (16) forming a tapped time delay line (12), said time delay line having one end thereof connected to the input terminal; a data input terminal (64) for accepting incoming data signals; means (54) for connecting said terminal (64) to said input terminal (14); means (52) for generating a first signal (A); means (56) for generating a second signal (C) in response to said first signal; means (60) responsive to said incoming data signals for generating a control signal (F); said means (54) responsive to said control signal (F) for disconnecting said data input terminal (64) and connecting said first signal (A) to the input terminal (14); means (22e-m) responsive to said first signal (A) at a plurality of selected locations along said time delay line (12) and responsive to said second signal (C) for providing one of a plurality of possible control signals in response to a predetermined relationship between said first (A) and said (C) signals; and a plurality of signal activated switches (36e-m), each switch being responsive to a corresponding one of said control signals for connecting a said selected tap (38e-m) of said time delay line (12) to said output terminal (41).

Claim 14

An adjustable time delay circuit (10, 50) of claim 9 wherein said delay line (12) comprises a plurality of serially connected inverters (16).