Frame arrangement for multiplexing a plurality of subchannels onto a fixed rate channel

Claim 3

The method in accordance with claim 1 wherein the frame length ij equals xQ where x is an integer and Q is the least common multiple of the denominators of the subchannel rates normalized by the fixed channel rate to an irreducible ratio, i≧ Q/L +1 where D is the difference between Q and the number of bits per Q bits required for all of said subchannels, ##EQU15## and j is an integer equal to (xQ)/i.

Claim 4

In a multiplier that multiplexes a plurality of digital subchannels onto a fixed rate digital channel by forming successive frames having a fixed number of bits framing apparatus that comprises: means for forming each frame so that it consists of j i-tuples of bits, i and j being mathematically predetermined as a function of the rates of each of said digital subchannels and the rate of said fixed rate digital channel, said forming means including means for setting in each frame each bit in one of said i-tuples to one predetermined binary digit, means for setting in each frame one fixed bit at one end of each of the other j-1 i-tuples to a predetermined binary digit opposite to the digit set as each bit of said one i-tuple, and means for distributing in each frame in a predetermined pattern in the remaining (i-1)(j-1) bit positions an integral number of bits from each of said subchannels.

Claim 5

In a multiplier that multiplexes a plurality of digital subchannels onto a fixed rate digital channel by forming successive frames having a fixed number of bits framing apparatus that comprises: means for forming each frame so that it consists of j i-tuples of bits, i and j being mathematically predetermined as a function of the rates of each of said digital subchannels and the rate of said fixed rate digital channel, said forming means including means for setting in each frame each bit in one of said i-tuples to one predetermined binary digit, means for setting in each frame one fixed bit at one end of each of the other j-1 i-tuples to a predetermined binary digit opposite to the digit set as each bit of said one i-tuple, and means for distributing in each frame in a predetermined pattern in the remaining (i-1)(j-1) bit positions an integral number of bits from each of said subchannels.

Claim 6

Framing apparatus in accordance with claim 3 wherein the frame length ij equals xQ where x is an integer and Q is the least common multiple of the denominators of the subchannel rates normalized by the fixed channel rate to an irreducible ratio, i≧ Q/D +1 where D is the difference between Q and the number of bits per Q bits required for all of said subchannels, ##EQU16## and j is an integer equal to (xQ)/i.

Claim 7

A multiplexer for multiplexing a plurality of digital subchannels onto a fixed rate digital channel by forming successive frames of bits comprising: a plurality of bit storage means, one storage means associated with each of said subchannels, each storage means for storing a predetermined number of bits from its associated subchannel, a selector responsive to a selection code for selecting either a bit stored in any of said plurality of storage means or a fixed binary ONE or ZERO digit, output means for forming a multiplexed output bit stream at said fixed rate from bits selected by said selector, and means for generating selection codes for each bit in said multiplexed output bit stream, said selection codes repeated in a predetermined pattern so that said multiplexed output bit stream consists of frames that include j i-tuples of bits, i and j being mathematically predetermined as a function of the rates of each of said digital subchannels and the rate of said fixed rate digital channel, said selection codes being such that in one in said i-tuples in each frame each bit selected is one of said fixed binary digits and in each of the other j-1 i-tuples in each frame one fixed bit at one end of the i-tuple is selected as the other of said fixed binary digits, and for the remaining (i-1)(j-1) bit positions in each frame said selection codes being such that an integral number of bits from each of said subchannels are selected.

Claim 8

A multiplexer for multiplexing a plurality of digital subchannels onto a fixed rate digital channel by forming successive frames of bits comprising: a plurality of bit storage means, one storage means associated with each of said subchannels, each storage means for storing a predetermined number of bits from its associated subchannel, a selector responsive to a selection code for selecting either a bit stored in any of said plurality of storage means or a fixed binary ONE or ZERO digit, output means for forming a multiplexed output bit stream at said fixed rate from bits selected by said selector, and means for generating selection codes for each bit in said multiplexed output bit stream, said selection codes repeated in a predetermined pattern so that said multiplexed output bit stream consists of frames that include j i-tuples of bits, i and j being mathematically predetermined as a function of the rates of each of said digital subchannels and the rate of said fixed rate digital channel, said selection codes being such that in one in said i-tuples in each frame each bit selected is one of said fixed binary digits and in each of the other j-1 i-tuples in each frame one fixed bit at one end of the i-tuple is selected as the other of said fixed binary digits, and for the remaining (i-1)(j-1) bit positions in each frame said selection codes being such that an integral number of bits from each of said subchannels are selected.

Claim 9

A multiplexer in accordance with claim 5 further comprising: means for deriving a clock signal at the least common integral rate of said plurality of subchannels and said fixed channel from a clock signal at said fixed rate, said means for generating said selection codes including counting means for repetitively counting clock pulses at said least common integral rate and memory means for generating each selection code as a function of the count of said counting means.

Claim 10

A multiplexer in accordance with claim 5 wherein the frame length ij equals xQ where x is an integer and Q is at least common multiple of the denominators of the subchannel rates normalized by the fixed channel rate to an irreducible ratio, i≧ Q/D +1 where D is the difference between Q and the number of bit per Q bits required for all of said subchannels, ##EQU17## and j is an integer equal to (xQ)/i.

Claim 11

A demultiplexer for demultiplexing a multiplexed bit stream from a fixed rate channel onto a plurality of digital subchannels, said multiplexed bit stream being formed from successive frames of bits, each frame including j i-tuples of bits, i and j being mathematically determined as a function of the rates of said digital subchannels and the rate of said fixed rate digital channel, in one of said i-tuples in each frame each bit being one predetermined binary digit and in each of the other j-1 i-tuples in each frame one fixed bit at one end of the i-tuple being an opposite binary digit, the remaining (i-1)(j-1) bit positions in each frame containing an integral number of bits for each of said subchannels, said demultiplexer comprising: means for determining the start of each frame by detecting from i+1 consecutive bits in said multiplexed bit stream i consecutive bits that are said one predetermined binary digit and one bit that is said opposite binary digit, and means for distributing the bits in said (i-1)(j-1) bit positions in each frame onto said plurality of digital subchannels.

Claim 12

A demultiplexer for demultiplexing a multiplexed bit stream from a fixed rate channel onto a plurality of digital subchannels, said multiplexed bit stream being formed from successive frames of bits, each frame including j i-tuples of bits, i and j being mathematically determined as a function of the rates of said digital subchannels and the rate of said fixed rate digital channel, in one of said i-tuples in each frame each bit being one predetermined binary digit and in each of the other j-1 i-tuples in each frame one fixed bit at one end of the i-tuple being an opposite binary digit, the remaining (i-1)(j-1) bit positions in each frame containing an integral number of bits for each of said subchannels, said demultiplexer comprising: means for determining the start of each frame by detecting from i+1 consecutive bits in said multiplexed bit stream i consecutive bits that are said one predetermined binary digit and one bit that is said opposite binary digit, and means for distributing the bits in said (i-1)(j-1) bit positions in each frame onto said plurality of digital subchannels.

Claim 13

A demultiplexer for demultiplexing a multiplexed bit stream from a fixed rate channel onto a plurality of digital subchannels, said multiplexed bit stream being formed from successive frames of bits, each frame including j i-tuples of bits, i and j being mathematically determined as a function of the rates of said digital subchannels and the rate of said fixed rate digital channel, in one of said i-tuples in each frame each bit being one predetermined binary digit and in each of the other j-1 i-tuples in each frame one fixed bit at one end of the i-tuple being an opposite binary digit, the remaining (i-1)(j-1) bit positions in each frame containing an integral number of bits for each of said subchannels, said demultiplexer comprising: storage means for storing a predetermined number of bits from said multiplexed bit stream, pattern detecting means for determining the start of each frame by detecting from i+1 consecutive bits in said multiplexed bit stream i consecutive bits that are said one predetermined binary digit and one bit that is said opposite binary digit, selection means responsive to selection codes for selecting bits from said storage means, plural output means for forming plural output bit streams onto said digital subchannels from the bits selected from said storage means, and means for generating said selection codes, a selection code generated for each bit in each of said output bit streams, said selection codes repeated in a predetermined pattern for each frame of bits in said multiplexed bit stream, the repeat of said pattern being responsive to the detection of the start of each frame by said pattern detecting means.

Claim 14

A demultiplexer for demultiplexing a multiplexed bit stream from a fixed rate channel onto a plurality of digital subchannels, said multiplexed bit stream being formed from successive frames of bits, each frame including j i-tuples of bits, i and j being mathematically determined as a function of the rates of said digital subchannels and the rate of said fixed rate digital channel, in one of said i-tuples in each frame each bit being one predetermined binary digit and in each of the other j-1 i-tuples in each frame one fixed bit at one end of the i-tuple being an opposite binary digit, the remaining (i-1)(j-1) bit positions in each frame containing an integral number of bits for each of said subchannels, said demultiplexer comprising: storage means for storing a predetermined number of bits from said multiplexed bit stream, pattern detecting means for determining the start of each frame by detecting from i+1 consecutive bits in said multiplexed bit stream i consecutive bits that are said one predetermined binary digit and one bit that is said opposite binary digit, selection means responsive to selection codes for selecting bits from said storage means, plural output means for forming plural output bit streams onto said digital subchannels from the bits selected from said storage means, and means for generating said selection codes, a selection code generated for each bit in each of said output bit streams, said selection codes repeated in a predetermined pattern for each frame of bits in said multiplexed bit stream, the repeat of said pattern being responsive to the detection of the start of each frame by said pattern detecting means.

Claim 15

A digital transmission system for transmitting a plurality of input bit streams on a plurality of digital input subchannels over a fixed rate digital channel by multiplexing at one end of said system said input bit streams to form a multiplexed bit stream and at the other end of said system demultiplexing said multiplexed bit stream to reform said input bit streams on a plurality of output subchannels comprising: at said one end, means for forming from said plurality of digital subchannels successive frames having a fixed number of bits, each of said frames consisting of j i-tuples, i and j being mathematically predetermined as a function of the rates of each of said digital input subchannels and the rate of said fixed rate digital channel, in one of said i-tuples in each frame each bit in being set to one predetermined binary digit and in each of the other j-1 i-tuples in each frame one fixed bit at one end of the j-1 i-tuple being set to an opposite binary digit, and an integral number of bits from each of said digital input subchannels being distributed in a predetermined pattern among the remaining (i-1)(j-1) bit positions in each frame, and at the other end, means for determining the start of each frame by detecting in i+1 consecutive bits in the multiplexed bit stream i consecutive bits that are said one predetermined binary digit and one bit that is said opposite binary digit, and means for distributing from each frame in a predetermined pattern the bits in said (i-1)(j-1) bit positions to said output subchannels.

Claim 16

A digital transmission system for transmitting a plurality of input bit streams on a plurality of digital input subchannels over a fixed rate digital channel by multiplexing at one end of said system said input bit streams to form a multiplexed bit stream and at the other end of said system demultiplexing said multiplexed bit stream to reform said input bit streams on a plurality of output subchannels comprising: at said one end, means for forming from said plurality of digital subchannels successive frames having a fixed number of bits, each of said frames consisting of j i-tuples, i and j being mathematically predetermined as a function of the rates of each of said digital input subchannels and the rate of said fixed rate digital channel, in one of said i-tuples in each frame each bit in being set to one predetermined binary digit and in each of the other j-1 i-tuples in each frame one fixed bit at one end of the j-1 i-tuple being set to an opposite binary digit, and an integral number of bits from each of said digital input subchannels being distributed in a predetermined pattern among the remaining (i-1)(j-1) bit positions in each frame, and at the other end, means for determining the start of each frame by detecting in i+1 consecutive bits in the multiplexed bit stream i consecutive bits that are said one predetermined binary digit and one bit that is said opposite binary digit, and means for distributing from each frame in a predetermined pattern the bits in said (i-1)(j-1) bit positions to said output subchannels.