Ring oscillator with delay element and potential pulling circuit

Claim 2

An oscillator circuit comprising: an odd number of inverters connected in cascade to form a loop; a delay element inserted between adjacent inverters; and a pulling circuit for pulling up the potential of the output terminal of said delay element during a predetermined period after the potential of said output terminal becomes higher than the threshold voltage of said inverter connected to the output terminal of said delay element and/or for pulling down the potential of said output terminal during a predetermined period after the potential of said output terminal becomes lower than said threshold voltage.

Claim 3

An oscillator circuit according to claim 1, wherein said delay element is an integration circuit consisting of a capacitance element and a resistance element.

Claim 4

An oscillator circuit according to claim 2, wherein said resistance element is constituted by an MOS type transistor and said capacitance element is constituted by an MOS capacitor.

Claim 5

An oscillator circuit according to claim 1, wherein said pulling circuit is constituted by transistors, said transistors being turned on or turned off in response to an inversion operation of one of said inverters.

Claim 6

An oscillator circuit according to claim 1, wherein each of said inverters, said delay element, and said pulling circuit is constituted by an MOS element.

Claim 7

An oscillator circuit according to claim 1, wherein each of said inverters, said delay element, and said pulling circuit is constituted by an NMOS element.

Claim 8

An oscillator circuit comprising: an odd number of inverters connected in cascade to form a loop; a delay element inserted between adjacent inverters in the loop; and a circuit for pulling up and pulling down the potential of the output terminal of the delay element alternately in response to the inversion operation of one of said inverters.

Claim 9

An oscillator circuit comprising: an odd number of inverters connected in cascade to form a loop; a delay element inserted between adjacent inverters in the loop; and a circuit for pulling up and pulling down the potential of the output terminal of the delay element alternately in response to the inversion operation of one of said inverters.

Claim 10

A substrate bias voltage generator comprising an oscillator circuit comprising: an odd number of inverters connected in cascade to form a loop; a delay element inserted between adjacent inverters; and a pulling circuit for pulling up the potential of the output terminal of said delay element during a predetermined period after the potential of said output terminal becomes higher than the threshold voltage of said inverter connected to the output terminal of said delay element and/or for pulling down the potential of said output terminal during a predetermined period after the potential of said output terminal becomes lower than said threshold voltage; and a charge pumping circuit for generating the substrate bias voltage connected to an output terminal of said oscillator circuit.

Claim 11

A substrate bias voltage generator comprising an oscillator circuit comprising: an odd number of inverters connected in cascade to form a loop; a delay element inserted between adjacent inverters; and a pulling circuit for pulling up the potential of the output terminal of said delay element during a predetermined period after the potential of said output terminal becomes higher than the threshold voltage of said inverter connected to the output terminal of said delay element and/or for pulling down the potential of said output terminal during a predetermined period after the potential of said output terminal becomes lower than said threshold voltage; and a charge pumping circuit for generating the substrate bias voltage connected to an output terminal of said oscillator circuit.