US4616315A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System memory for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
Assignee: Unisys Corp
•
Filing: 1985-01-11
•
Granted: 1986-10-07
•
Expires: 2005-01-11
Abstract
Abstract A system memory for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. In order to accommodate the scanning of a number of storage locations in parallel, the system memory is divided into a node memory and the mark bit memory so that the mark bits for a number of sequential storage locations can be examined in parallel to determine which node locations are free for use by the graph manager.
Inventors
- 👤 Gary L. Logsdon
- 👤 Mark R. Scheevel
- 👤 Michael A. Winchell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:06
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4494
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
85 words
A processing system including: a storage location memory having a plurality of storage locations; a mark bit memory containing a plurality of mark bit positions each of which corresponds to a storage location in said storage location memory to indicate that that location has been allocated when the mark bit has been set and that the corresponding storage location is available for use when the mark bit has been reset; and bus means coupled to both memories to access at least one of said memories.
Claim 2
Dependent Claim
85 words
A processing system including: a storage location memory having a plurality of storage locations; a mark bit memory containing a plurality of mark bit positions each of which corresponds to a storage location in said storage location memory to indicate that that location has been allocated when the mark bit has been set and that the corresponding storage location is available for use when the mark bit has been reset; and bus means coupled to both memories to access at least one of said memories.
Claim 3
Dependent Claim
34 words
A system according to claim 1 further including: memory accessing means coupled by said bus means to said memory of storage locations and to said mark bit memory for accessing both memories in parallel.
Claim 4
Dependent Claim
23 words
A system according to claim 1 further including: mark bit accessing means coupled to said bus means for accessing said mark bit memory.
Claim 5
Dependent Claim
35 words
A system according to claim 1 wherein: said mark bit accessing means includes parallel addressing means to access a plurality of mark bits representing a plurality of sequential storage locations in said storage location memory.
Claim 6
Dependent Claim
26 words
A system according to claim 3 wherein said mark bit accessing means includes means for accessing a single mark bit position in said mark bit memory.
Claim 7
Dependent Claim
109 words
A processing system comprising: a memory of storage locations; a mark bit memory having a plurality of marked bit positions each of which corresponds to one of said storage locations in said memory, which mark bit positions when set indicate that the corresponding storage location has been allocated and when reset indicates that the corresponding storage location is available for use; processing means coupled to both said memory of storage locations and said mark bit memory; and allocation means coupled to said mark bit memory and said processing means for testing said mark bit positions for locations of available storage locations and transmitting their addresses to said processing means.
Claim 8
Dependent Claim
109 words
A processing system comprising: a memory of storage locations; a mark bit memory having a plurality of marked bit positions each of which corresponds to one of said storage locations in said memory, which mark bit positions when set indicate that the corresponding storage location has been allocated and when reset indicates that the corresponding storage location is available for use; processing means coupled to both said memory of storage locations and said mark bit memory; and allocation means coupled to said mark bit memory and said processing means for testing said mark bit positions for locations of available storage locations and transmitting their addresses to said processing means.
Claim 9
Dependent Claim
30 words
A system according to claim 6 further including: memory accessing means coupled to said memory of storage locations and to said mark bit memory for accessing both memories in parallel.
Claim 10
Dependent Claim
18 words
A system according to claim 6 further including: mark bit accessing means for accessing said mark bit memory.
Claim 11
Dependent Claim
35 words
A system according to claim 8 wherein: said mark bit accessing means includes parallel addressing means to access a plurality of mark bits representing a plurality of sequential storage locations in said storage location memory.
Claim 12
Dependent Claim
26 words
A system according to claim 8 wherein said mark bit accessing means includes means for accessing a single mark bit position in said mark bit memory.
References Cited (Backward Citations)
US3469239A
Cited
US4121286A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-06 | 1990-04-07 | 1990-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-06 | 1994-04-07 | 1994-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-06 | 1998-04-07 | 1998-10-07 | $7700.00 | Window Closed / Lapsed |