Multiplying circuit comprising switched-capacitor circuits

Claim 1

In a multiplying circuit for multiplying a first signal x(t) by a periodic second signal y(t) to produce a product signal z(t), such multiplying circuit comprising: a plurality N of signal channels for receiving the first signal, each such signal channel comprising: a switched-capacitor circuit which is switched by control pulses g(k,i) applied thereto of finite duration so as to convert the first signal into a sequence of pulses, where k is the number of the signal channel and k=0, 1, 2, . . . N-1, and i= . . . -2, -1, 0, 1, 2, 3, . . . ; and means connected to such switched-capacitor circuit for weighting the relative amplitudes of such sequence of pulses in accordance with a constant weighting factor W(k) such that W(k)=y(t 0 +k(T 0 /N), where T 0 and t 0 are constants, and for converting such pulses into pulses of predetermined duration, the resultant sequence of pulses being the channel output signal; pulse generating means connected to each of said signal channels for producing said control pulses g(k,i) with a repetition period T 0 and at instants t 0 +k(T 0 /N)+iT 0 ; and means connected to said N signal channels for combining the channel output signals produced thereby, the combination of said signals being the product signal z(t); such multiplying circuit being characterized in that said means for combining the N channel output signals comprises: means for adding the N channel output signals to generate a sum signal; and a sampling circuit for sampling the sum signal during the intervals between successive control pulses, such sampled sum signal being the product signal z(t).