US4615766A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Silicon cap for annealing gallium arsenide
Assignee: International Business Machines Corp
•
Filing: 1985-02-27
•
Granted: 1986-10-07
•
Expires: 2005-02-27
Abstract
Abstract A method of manufacturing GaAs semiconductor devices includes the steps of emplacing doping impurities by ion implantation on at least one surface of a GaAs substrate, and a step of annealing to remove damage resulting from the implantation of the impurities in the GaAs material. Prior to the annealing, a silicon capping layer is deposited on the surface by either sputtering, evaporation, or vapor deposition to a thickness of 100-10,000 angstroms. Subsequent to the annealing, the silicon capping layer is removed by etching. The silicon cap prevents out-diffusion of arsenic from the GaAs, and has a coefficient of thermal expansion which is sufficiently close to that of the GaAs to inhibit the formation of cracks in the capping layer.
Inventors
- 👤 Thomas N. Jackson
- 👤 Gwen Pepper
- 👤 Richard F. Rutz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:49
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/20; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P95/00; H10P95/90; H10P95/904; Y; Y10; Y10S; Y10S148/00; Y10S148/084; Y10S438/00; Y10S438/902
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
58 words
A method of forming an ion implanted GaAs device comprising: implanting ions into at least one surface of a GaAs substrate; depositing a capping layer of silicon upon said one surface; annealing said substrate, said capping layer retaining arsenic in said GaAs during said annealing; and etching said silicon capping layer to remove the silicon from said substrate.
Claim 2
Independent Claim
58 words
A method of forming an ion implanted GaAs device comprising: implanting ions into at least one surface of a GaAs substrate; depositing a capping layer of silicon upon said one surface; annealing said substrate, said capping layer retaining arsenic in said GaAs during said annealing; and etching said silicon capping layer to remove the silicon from said substrate.
Claim 3
Dependent Claim
29 words
A method according to claim 1 wherein said annealing is done at an elevated temperature of approximately 700-1200 celsius for a duration of approximately 1 nanosecond to 100 minutes.
Claim 4
Dependent Claim
26 words
A method according to claim 1 wherein in said step of depositing, said capping layer is deposited to a thickness in the range of 100-10,000 angstroms.
Claim 5
Dependent Claim
13 words
A method according to claim 1 wherein said etching employs a fluorine-based etchant.
Claim 6
Independent Claim
69 words
A method of forming an ion implanted GaAs device comprising: implanting ions into at least one surface of a GaAs substrate; depositing a capping layer of silicon upon said surface to a thickness in the range of 100-10,000 angstroms; annealing said substrate, said capping layer retaining arsenic in said GaAs during said annealing; and etching said silicon capping layer with fluorine-based etchant to remove the silicon from said substrate.
Claim 7
Independent Claim
69 words
A method of forming an ion implanted GaAs device comprising: implanting ions into at least one surface of a GaAs substrate; depositing a capping layer of silicon upon said surface to a thickness in the range of 100-10,000 angstroms; annealing said substrate, said capping layer retaining arsenic in said GaAs during said annealing; and etching said silicon capping layer with fluorine-based etchant to remove the silicon from said substrate.
Claim 8
Dependent Claim
18 words
A method according to claim 5 wherein said annealing is done at a temperature up to 1200° Celsius.
Claim 9
Dependent Claim
23 words
A method according to claim 5 wherein said surface is cleaned and polished before said step of depositing said caping layer of silicon.
Claim 10
Dependent Claim
34 words
A method according to claim 5 wherein said depositing is accomplished by sputtering silicon, evaporating silicon, or by vapor deposition of silicon onto said surface of said substrate to form an adhering layer thereon.
Claim 11
Dependent Claim
33 words
A method according to claim 8 wherein said annealing is done at a temperature in the range of 700°-1200° Celsius with a duration of annealing time being approximately 1 nanosecond to 100 minutes.
Claim 12
Dependent Claim
88 words
In a process of establishing a localized distribution of impurities in a gallium arsenide semiconductor crystal through implantation of ions followed by annealing, the improvement comprising: applying a capping layer of silicon over the surface of said gallium arsenide crystal; through which crystal said ions were implanted into said crystal; and subjecting the combination of said crystal and said silicon layer to an annealing temperature cycle in an ambient free from over pressure of arsenic, said capping layer retaining arsenic in said GaAs during said annealing temperature cycle.
Claim 13
Dependent Claim
88 words
In a process of establishing a localized distribution of impurities in a gallium arsenide semiconductor crystal through implantation of ions followed by annealing, the improvement comprising: applying a capping layer of silicon over the surface of said gallium arsenide crystal; through which crystal said ions were implanted into said crystal; and subjecting the combination of said crystal and said silicon layer to an annealing temperature cycle in an ambient free from over pressure of arsenic, said capping layer retaining arsenic in said GaAs during said annealing temperature cycle.
Claim 14
Dependent Claim
34 words
In a process according to claim 10, the improvement further comprising the step of etching the silicon of said silicon capping layer with fluorine-based etchant for removal of the silicon from said semiconductor crystal.
Claim 15
Dependent Claim
51 words
In a process according to claim 10 the improvement wherein said applying of the capping layer provides a layer thickness in the range of 100-10,000 angstroms, and wherein said annealing is accomplished in a temperature range of approximately 700°-1200° Celsius over a time duration of approximately 1 nanosecond to 100 minutes.
References Cited (Backward Citations)
US4267014A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-06 | 1990-04-07 | 1990-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-06 | 1994-04-07 | 1994-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-06 | 1998-04-07 | 1998-10-07 | $7700.00 | Window Closed / Lapsed |