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US4615019A
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Data processing system with interrupt facilities
Assignee: TIM SpA
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Filing: 1982-10-28
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Granted: 1986-09-30
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Expires: 2002-10-28
Abstract
Abstract The system comprises a series of input-output units (I/O) connected by means of a bus (21) to a central unit (CPU) capable of accepting at least one category of vectored interrupts requested by the I/O units and a category of non-vectored interrupts. The vectored interrupts are divided into at least two levels in which relative priority between units belonging to the same level depends on the position of the respective connection to a conductor of the bus. Performance of an interrupt is carried out by means of a routine which includes a closing tail. The performance of a series of interrupts of the same level may be carried out serially by suppressing the tail of all the routines except the last. The non-vectored interrupts are divided into a plurality of levels which are defined by the content of a register which is capable of being variably loaded by means of a suitable instruction. The content of the register in turn addresses a specific routine for performance of the interrupt. The I/O unit may also be connected for direct access to a common memory (RAM) with a priority defined by the position of the respective connection to another conductor of the bus.
Inventors
- 👤 Franco Bonci
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F13/00; G06F13/14; G06F13/20; G06F13/32; G06F13/34
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
213 words
A data processing system including a central processing unit, a plurality of input-output units connected to said central processing unit by means of a system bus, a plurality of circuits for generating corresponding vectored interrupts for said central processing unit, each one of said circuits being associated with one of said input-output units, wherein the improvement includes first means for connecting a first group of said circuits in a first daisy chain departing from the central processing unit to generate interrupts of a higher level in such a manner that the relative priority of the associated input-output units depends on the relative position of the connection in said first daisy chain in a predetermined direction, second means for connecting a second group of said circuits in a second daisy chain departing from said central processing unit to generate interrupts of a lower level in such a manner that the relative priority of the associated input-output units depends on the relative position of the connection in said second daisy chain in a direction opposite to said predetermined direction, and means for directly connecting the circuit generating the interrupt of the lowest relative priority in said first daisy chain with the circuit generating the interrupt of the highest relative priority in said second daisy chain.
Claim 2
Dependent Claim
213 words
A data processing system including a central processing unit, a plurality of input-output units connected to said central processing unit by means of a system bus, a plurality of circuits for generating corresponding vectored interrupts for said central processing unit, each one of said circuits being associated with one of said input-output units, wherein the improvement includes first means for connecting a first group of said circuits in a first daisy chain departing from the central processing unit to generate interrupts of a higher level in such a manner that the relative priority of the associated input-output units depends on the relative position of the connection in said first daisy chain in a predetermined direction, second means for connecting a second group of said circuits in a second daisy chain departing from said central processing unit to generate interrupts of a lower level in such a manner that the relative priority of the associated input-output units depends on the relative position of the connection in said second daisy chain in a direction opposite to said predetermined direction, and means for directly connecting the circuit generating the interrupt of the lowest relative priority in said first daisy chain with the circuit generating the interrupt of the highest relative priority in said second daisy chain.
Claim 3
Dependent Claim
105 words
A system according to claim 1, wherein said daisy chain connections are included in said system bus, and wherein the relative priority of the interrupts generated by the circuits of said first group decreases with the connection from said central processing unit while the relative priority of the interrupts generated by the circuits of said second group increases with the distance of the connection from said central processing unit, each one of said circuits including means effective upon generation of the relevant interrupt for connecting the two daisy chains together at the distance of the connection of the relevant circuit from said central processing unit.
Claim 4
Dependent Claim
49 words
A system according to claim 2, comprising an additional input-output unit, control means for alternately connecting said additional input-output unit with said daisy chains, and signal generating means included in said additional input-output unit for causing said control means to select one of said daisy chains for the connection.
Claim 5
Dependent Claim
44 words
A system according to claim 3, wherein said additional input-output unit includes a printer, said control means so alternately connecting said printer as to have the highest relative priority in said first daisy chain or the lowest relative priority in said second daisy chain.
Claim 6
Dependent Claim
76 words
A system according to claim 2, including third means for connecting a third group of said circuits in a third daisy chain in such a manner that the relative priority of the associated input-output units depends on the relative position of the connection in said third daisy chain, and means conditioned by the interrupts generated by the circuits of said first and second group for masking the interrupts generated by the circuits of said third group.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-29 | 1990-03-31 | 1990-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-29 | 1994-03-31 | 1994-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-29 | 1998-03-31 | 1998-09-30 | $7700.00 | Window Closed / Lapsed |