US4613905A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video noise reduction circuit having improved transient characteristics
Assignee: Victor Company of Japan Ltd
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Filing: 1985-11-22
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Granted: 1986-09-23
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Expires: 2005-11-22
Abstract
Abstract In a noise reduction circuit an input video signal is applied to a pair of low-pass filters having high and low time constant values to reject noise components, the noise-free output of the low-pass filter having the smaller time constant being scaled down and combined with the noise-free output of the filter having the high constant value. The input video signal is concurrently delayed with respect to the signal applied to the low-pass filters and applied to a differential amplifier where a difference between them is detected and fed to a limiter to generate an offset voltage. This offset voltage is destructively combined with the delayed video signal.
Inventors
- 👤 Yutaka Ichinoi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 10:58
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
286 words
A noise reduction circuit having an input terminal to which a video signal is applied and an output terminal, comprising: a noise rejection low-pass filter having a predetermined rise time for rejecting noise introduced in the video signal applied to said input terminal; waveform shaping means comprising a second low-pass filter having a rise time smaller than said predetermined rise time and an attenuator connected in series therewith for generating an output signal having an uphill slope portion during a transition of the video signal from a first level to a second level and a downhill slope portion during a transition from said second level to said first level; an adder for summing the output signal of the noise-rejection filter and the output signal of said waveshaping means; a first differential amplifier having a first input terminal responsive to an output signal from said adder and a second input terminal; means connecting the input terminal of the noise reduction circuit to said first and second low-pass filters and to the second input terminal of said first differential amplifier, said connecting means including delay means for introducing a delay so that a video signal applied to said first and second low-pass filters is advanced by an amount equal to said predetermined rise time with respect to a video signal applied to said second input terminal of said first differential amplifier; a limiter connected to the output of said first differential amplifier to detect small-amplitude noise; and a second differential amplifier having a first input terminal responsive to said small-amplitude noise and a second input terminal responsive to the video signal applied to said input terminal of the noise reduction circuit for canceling noise in said video signal.
Claim 2
Dependent Claim
286 words
A noise reduction circuit having an input terminal to which a video signal is applied and an output terminal, comprising: a noise rejection low-pass filter having a predetermined rise time for rejecting noise introduced in the video signal applied to said input terminal; waveform shaping means comprising a second low-pass filter having a rise time smaller than said predetermined rise time and an attenuator connected in series therewith for generating an output signal having an uphill slope portion during a transition of the video signal from a first level to a second level and a downhill slope portion during a transition from said second level to said first level; an adder for summing the output signal of the noise-rejection filter and the output signal of said waveshaping means; a first differential amplifier having a first input terminal responsive to an output signal from said adder and a second input terminal; means connecting the input terminal of the noise reduction circuit to said first and second low-pass filters and to the second input terminal of said first differential amplifier, said connecting means including delay means for introducing a delay so that a video signal applied to said first and second low-pass filters is advanced by an amount equal to said predetermined rise time with respect to a video signal applied to said second input terminal of said first differential amplifier; a limiter connected to the output of said first differential amplifier to detect small-amplitude noise; and a second differential amplifier having a first input terminal responsive to said small-amplitude noise and a second input terminal responsive to the video signal applied to said input terminal of the noise reduction circuit for canceling noise in said video signal.
Claim 3
Dependent Claim
72 words
A noise reduction circuit as claimed in claim 1, further comprising: second waveform shaping means connected from the output of said second low-pass filter for generating an output signal; and a third differential amplifier for combining the output signals of said second differential amplifier and the output signal of said second waveform shaping means to generate a noise-suppressed video signal to be applied to said output terminal of the noise reduction circuit.
Claim 4
Dependent Claim
98 words
A noise reduction circuit as claimed in claim 2, wherein said second waveform shaping means comprises: second and third delay circuits having different delay times; and second and third attenuators respectively connected in series with said second and third delay circuits from the output of said second low-pass filter to generate first and second portions of the output signal of said second waveform shaping means; and a second adder for summing said first and second portions to generate the output signal of said second waveform shaping means and applying the last-mentioned output signal to said third differential amplifier.
References Cited (Backward Citations)
US4302768A
Cited
US4393396A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-22 | 1990-03-24 | 1990-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-22 | 1994-03-24 | 1994-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-22 | 1998-03-24 | 1998-09-23 | $7700.00 | Window Closed / Lapsed |